CY26049ZXC-20 datasheet, PDF - EEWORLD Datasheet

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CY26049ZXC-20: DescriptionClock Generators u0026 Support Products FailSafe Clock COM; Categorysemiconductor Analog mixed-signal IC; File Size1MB，12 Pages; ManufacturerCypress Semiconductor

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CY26049ZXC-20 Overview

Clock Generators u0026 Support Products FailSafe Clock COM

CY26049ZXC-20 Parametric

Parameter Name	Attribute value
Product Category	Clock Generators & Support Products
Manufacturer	Cypress Semiconductor
RoHS	Details
Type	Clock Generators
Moisture Sensitive	Yes
Factory Pack Quantity	96

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CY26049-36

FailSafe™ PacketClock

Global Communications Clock Generator

FailSafe™ PacketClock Global Communications Clock Generator

Features

■

Functional Description

CY26049 is a FailSafe frequency synthesizer with a reference

clock input and three clock outputs. The device provides an

optimum solution for applications which require continuous

operation in case of primary clock failure. The continuous,

glitch-free operation is achieved by using a DCXO which serves

as a primary clock source. The FailSafe control circuit

synchronizes the DCXO with the reference as long as the

reference is within the pull range of the crystal.

In the event of a reference clock failure the DCXO maintains the

last frequency and phase information of the reference clock. The

unique feature of the CY26049-36 is that the DCXO is, in fact,

the primary clocking source. When the reference clock is

restored, the DCXO automatically resynchronizes to the

reference. The status of the reference clock input, as detected

by the CY26049-36, is reported by the SAFE pin.

In the buffer mode (FS3:FS0 = 1110 or 1111), the CY26049-36

can be used as a jitter attenuator. In this mode, extensive jitter

on the input clock is ‘filtered’, resulting in a low jitter output clock.

For a complete list of related documentation, click

here.

Fully Integrated Phase-Locked Loop (PLL)

FailSafe Output

8 kHz Reference Clock

PLL Driven by a Crystal Oscillator that is Phase Aligned with

External Reference

Selectable Standard Communication Output Frequencies

Low Jitter, High Accuracy Outputs

3.3 V Operation

16-pin TSSOP Package

Commercial and Industrial Temperature Ranges

Logic Block Diagram

external pullable crystal

(18.432 MHz)

XIN

Input reference

(typical 8 kHz)

ICLK

FAILSAFE

CONTROL

XOUT

DIGITAL

CONTROLLED

CRYSTAL

OSCILLATOR

PHASE

LOCKED

LOOP

CLK

OUTPUT

DIVIDERS

CLK/2

FS[3:0]

frequency select

SAFE

High=ICLK detected

Cypress Semiconductor Corporation

Document Number: 38-07415 Rev. *I

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised May 23, 2016

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