Digital VLSI Design (RTL to GDS)

Bar-Ilan University 83-612: Digital VLSI Design

In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).

Lecture slides can be found on the EnICS Labs web site at: 
https://enicslabs.com/academic-courses/dvd-english/

• Chapter 1：1a Introduction (10 minutes and 2 seconds)

• Chapter 2：1b Building a Chip (13 minutes and 50 seconds)

• Chapter 3：1c Design Automation (5 minutes and 42 seconds)

• Chapter 4：1d The Chip Design Flow (18 minutes and 0 seconds)

• Chapter 5：Introduction (16 minutes and 36 seconds)

• Chapter 6：2a_ Verilog (6 minutes and 9 seconds)

• Chapter 7：2b_ Verilog Syntax (29 minutes and 28 seconds)

• Chapter 8：2c_ Simple Verilog Examples (14 minutes and 40 seconds)

• Chapter 9：2d_ Verilog FSM Implementation (21 minutes and 6 seconds)

• Chapter 10：2e- Coding Style for RTL - part 1 (21 minutes and 6 seconds)

• Chapter 11：How to write Synthesizeable RTL (34 minutes and 51 seconds)

• Chapter 12：Verilog HDL (29 minutes and 45 seconds)

• Chapter 13：3a_ Logic Synthesis - Part 1 (13 minutes and 9 seconds)

• Chapter 14：3b_ HDL Compilation (2 minutes and 44 seconds)

• Chapter 15：3c- Library Definition (31 minutes and 51 seconds)

• Chapter 16：3d-LEF (12 minutes and 3 seconds)

• Chapter 17：3e_ Liberty (.lib) (14 minutes and 20 seconds)

• Chapter 18：3f- Contents of Standard Cell Libraries (4 minutes and 0 seconds)

• Chapter 19：Logic Synthesis Part 1 (18 minutes and 34 seconds)

• Chapter 20：4a_ Logic Synthesis - Part 2 (17 minutes and 34 seconds)

• Chapter 21：4b_ BDDs and Boolean Minimization (15 minutes and 29 seconds)

• Chapter 22：4c_ Constraint Definition (2 minutes and 8 seconds)

• Chapter 23：4d_ Technology Mapping (21 minutes and 28 seconds)

• Chapter 24：4e_ Verilog for Synthesis - revisited (16 minutes and 32 seconds)

• Chapter 25：4f- Timing Optimization (8 minutes and 50 seconds)

• Chapter 26：Logic Synthesis Part 2 (24 minutes and 14 seconds)

• Chapter 27：5a_ Timing Analysis (10 minutes and 59 seconds)

• Chapter 28：5b_ Timing Constraints (14 minutes and 38 seconds)

• Chapter 29：5c_ Static Timing Analysis (STA) (18 minutes and 17 seconds)

• Chapter 30：5d_ STA Example (12 minutes and 49 seconds)

• Chapter 31：5e_ Design Constraints (SDC) (9 minutes and 19 seconds)

• Chapter 32：5f_ SDC Continued. (22 minutes and 58 seconds)

• Chapter 33：5g_ Timing Reports (18 minutes and 51 seconds)

• Chapter 34：5h_ Multi-Mode Multi-Corner (MMMC) (15 minutes and 49 seconds)

• Chapter 35：Timing Analysis (41 minutes and 25 seconds)

• Chapter 36：6a_ Moving to the Physical Domain (6 minutes and 57 seconds)

• Chapter 37：6b- Multiple Voltage Domains (7 minutes and 16 seconds)

• Chapter 38：6c_ Floorplanning (22 minutes and 26 seconds)

• Chapter 39：6d_ Hierarchical Design (9 minutes and 59 seconds)

• Chapter 40：6e- Power Planning (19 minutes and 50 seconds)

• Chapter 41：Moving to the Physical Domain (24 minutes and 43 seconds)

• Chapter 42：7a_ Standard Cell Placement (6 minutes and 59 seconds)

• Chapter 43：7b_ Random Placement (14 minutes and 34 seconds)

• Chapter 44：7c_ Analytic Placement (14 minutes and 50 seconds)

• Chapter 45：7d- Analytic Placement Example (14 minutes and 35 seconds)

• Chapter 46：7e_ Placement in Practice (12 minutes and 27 seconds)

• Chapter 47：Placement (29 minutes and 15 seconds)

• Chapter 48：8a_ Clock Tree Synthesis (CTS) (19 minutes and 18 seconds)

• Chapter 49：8b_ Clock Distribution (16 minutes and 59 seconds)

• Chapter 50：8c_ Clock Concurrent Optimization (CCOpt) (9 minutes and 40 seconds)

• Chapter 51：8d- Clock Tree Synthesis in EDA Tools (10 minutes and 55 seconds)

• Chapter 52：8e_ Clock Routing and Clock Tree Analysis (12 minutes and 23 seconds)

• Chapter 53：8f_ Clock Generation (4 minutes and 47 seconds)

• Chapter 54：8g_ Clock Domain Crossing (CDC) (8 minutes and 26 seconds)

• Chapter 55：CTS (39 minutes and 22 seconds)

• Chapter 56：9a- Routing (3 minutes and 9 seconds)

• Chapter 57：9b_ Maze Routing (11 minutes and 37 seconds)

• Chapter 58：9c_ Maze Routing (continued) (12 minutes and 59 seconds)

• Chapter 59：9d- Routing in Practice (10 minutes and 37 seconds)

• Chapter 60：9e- Signal Integrity (SI) and Design for Manufacturing (DFM) (19 minutes and 12 seconds)

• Chapter 61：Routing (29 minutes and 52 seconds)

• Chapter 62：10a- Packaging (17 minutes and 17 seconds)

• Chapter 63：10b- I_O Circuits - Digital IOs (15 minutes and 44 seconds)

• Chapter 64：10c- I_O Circuits - Analog IOs, ESD Protection, Pad Configurations (14 minutes and 35 seconds)

• Chapter 65：10d- System-in-Package (SiP) (7 minutes and 23 seconds)

• Chapter 66：I_O and Packaging (39 minutes and 15 seconds)

• Chapter 67：11a_ Sign-off Timing (13 minutes and 3 seconds)

• Chapter 68：11b- Additional issues in Sign-off Timing (11 minutes and 25 seconds)

• Chapter 69：11c_ Chip Finishing, including Density Fill and Antenna Fixes (11 minutes and 21 seconds)

• Chapter 70： 11d- Sign-off Validation, including IR Drop and EM Analysis, LEC, and DRC_LVS_ERC (18 minutes and 53 seconds)

• Chapter 71：Chip Finishing and Signoff (32 minutes and 33 seconds)

• Chapter 72：Introduction to Tcl-The tool command language-Part1 (18 minutes and 5 seconds)

• Chapter 73：Introduction to Tcl-The tool command language-Part2 (15 minutes and 3 seconds)