Location:Training / Tools/EDA / Digital VLSI Design (RTL to GDS) / 8a_ Clock Tree Synthesis (CTS)

Bar-Ilan University 83-612: Digital VLSI Design

In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).

Lecture slides can be found on the EnICS Labs web site at: 
https://enicslabs.com/academic-courses/dvd-english/