• You can log in to your eeworld account to continue watching:
  • Lecture 56
  • Login
  • Duration:1 minutes and 1 seconds
  • Date:2016/11/15
  • Uploader:量子阱
Introduction
The basic theory, basic concepts, basic analysis methods, algorithms, and designs of digital signal processing are systematically discussed. The course consists of four parts. The first part is the basic concepts of discrete time signals (sequences) and systems and the analysis methods and algorithms of time domain and frequency domain (including z-transform domain), including discrete Fourier transform and its fast algorithm, and digital signal processing of analog signals. Principles and methods; the second part is the basic concepts, theories, structures and design methods of various IIR and FIR digital filters; the third part is the basic theory of multi-sampling rate digital signal processing; the fourth part is the implementation of digital signal processing Limited word length effect.

The supporting textbook "Digital Signal Processing Tutorial" by Tsinghua University Press is written by Cheng Peiqing.
Unfold ↓

You Might Like

Recommended Posts

The growth path of a logic engineer-About the industry
[align=left]I have been interviewing for a few months and received hundreds of resumes. I have interviewed dozens of people. Looking back, the people who submitted resumes can be divided into the foll
yifeilw FPGA/CPLD
[Sample photos] + Wireless charging and human proximity detection
[i=s] This post was last edited by yangshoot on 2015-2-27 21:09 [/i]This time I applied for [p=24, null, Qi (WPC) compliant for low power wearable applications Standard wireless charger (TIDA-00318)[/
yangshoot TI Technology Forum
cortex m3 NVIC
The offset address of the priority register defined in the "Cortex M3 Authoritative Guide" is 0x400, that is, 0xE000E400-->0xE000E4EF; the address of the ACTIVE register group is 0xE000E300-->0xE000E3
gzzhang Microcontroller MCU
C6713 programming help, there is CODE_SECTION
I plan to put part of the program into the SDRAM of CE0 port, so I used #pragma CODE_SECTION(counting,".xxxsect") and put the .xxxsect segment into SDRAM in the .cmd file. The compilation, linking and
gaayzq DSP and ARM Processors
Timing constraint information (with content description, a lot of information, package download)
These are some materials I collected when I was studying time series. Some of them may have been seen by everyone. They include some basic text materials and the contents of some personal blogs of onl
linhaiqing60 FPGA/CPLD
How long does it take to initialize LPC-Link for the first time?
How long does it take for LPC-Link to initialize for the first time? As the title says, I am using Windows XP SP3 English Edition, and the entire program becomes "unresponsive" once I connect to LPC-L
jobszheng5 NXP MCU

Recommended Content

Circuit

可能感兴趣器件

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号