Circuit functions and advantages

Need a small package, ultra-low power solution that delivers true 16-bit level setting performance? For precision 16 digital-to-analog conversion applications, this circuit uses the voltage output DAC AD5542A / AD5541A , the reference voltage source ADR421BRZ , and the 20 μA AD8657 as the reference voltage buffer   , providing a low-power, small-footprint solution.

Reference buffering is critical to the design because the input impedance of the DAC reference input is highly code-dependent, resulting in linearity errors if the DAC reference source is not adequately buffered. The AD8657, with up to 120 dB open loop gain, has been verified and tested to meet the settling time, offset voltage, and low impedance drive capability requirements of this circuit application.

The device combination shown in Figure 1 achieves the smallest PCB area and lowest power consumption. The AD5542A is available in a 3 mm × 3 mm, 16-lead LFCSP or 16-lead TSSOP package. The AD5541A is available in a 3 mm × 3 mm, 10-lead LFCSP or 10-lead MSOP package.

This combination of devices delivers industry-leading 16-bit resolution, ±1 LSB integral nonlinearity (INL) and ±1 LSB differential nonlinearity (DNL), ensuring monotonicity, along with low power consumption, a small PCB and high cost performance and other characteristics.

Circuit description

For an ideal DAC with no error, the output voltage is related to the reference voltage as follows:

Where D is the decimal data word loaded into the DAC register, and N is the resolution of the DAC.

For a 2.5 V reference voltage and N = 16, the above equation simplifies to the following:

_{This gives VOUT} 1.25 V at midscale and 2.5 V at full scale.

The LSB size is 2.5 V/65,536 = 38.1 μV.

At 16 bits, 1 LSB is also equivalent to 0.0015% of full scale, or 15 ppm FS.

The ADR421 voltage reference (Grade B) has an initial room temperature accuracy of 0.04%, which is equivalent to approximately 27 LSB at 16 bits. This initial error can be eliminated through system calibration. The ADR421 (Grade B) has a temperature coefficient of 1 ppm/°C typical and 3 ppm/°C maximum.

Assuming an ideal reference is used (reference error has been eliminated by system calibration), the worst-case unipolar output voltage of the AD5542A (including error) can be calculated as:

Where:
V _OUT−UNI is the worst-case output in unipolar mode.
D is the code loaded into the DAC.
V _REF is the reference voltage applied to the DAC (assuming no error).
V _GE is the gain error in volts (V). (Note that the offset error of the reference buffer must be included in the gain error, so the op amp selected for the reference buffer must have low input offset voltage characteristics.)
V _ZSE is the zero-level error (offset error) in volts (V ). (Note that the offset voltage of the optional output buffer amplifier will add to this error.)
INL is the integral nonlinearity of the DAC in volts (V). (Note that the nonlinearity of the optional output buffer amplifier can increase this error.)

This circuit uses the voltage output DAC AD5542A, which provides true 16-bit INL and DNL. The DAC architecture of the AD5541A/AD5542A is a segmented R-2R voltage mode DAC. With this configuration, the output impedance is code independent, while the input impedance of the reference is highly code dependent. Therefore, the selection of the reference voltage buffer is very important for the handling of code-dependent reference current. If the DAC reference voltage buffer is insufficient, linearity errors may result. The op amp's open-loop gain, offset voltage, offset error temperature coefficient, and voltage noise are also important selection criteria when selecting a reference voltage buffer for use with a precision voltage output DAC. Offset errors in the reference circuit can cause gain errors at the DAC output.

This circuit uses the AD8657 low-power CMOS op amp in a drive/sense configuration (Kelvin sensing) as the low-impedance output reference voltage buffer for the AD5542A. The AD8657 has an open-loop gain of 120 dB and is a precision, 18 V, 50 nV/√Hz operational amplifier. With a maximum offset voltage of 350 µV, typical temperature drift of less than 2 µV/°C, and noise of 5 µV pp (0.1 Hz to 10 Hz), the AD8657 is ideally suited for applications requiring minimal error sources. The other half of the AD8657 is used as the output amplifier. AD5542A has two operating modes: buffered mode and non-buffered mode. Which operating mode is used depends on the specific application and its settling time, load impedance, noise, etc. requirements. The output buffer can be selected to optimize DC accuracy or fast settling time. The output impedance of the DAC is constant (typically 6.25 kΩ) and is code independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The output amplifier should also have a 3 dB bandwidth of 1 MHz or higher. The output amplifier adds another time constant to the system, thus extending the settling time of the output. The wider the bandwidth of the op amp, the shorter the effective settling time of the DAC and amplifier combination.

The device combination shown in Figure 1 achieves minimal PCB area. The AD5542A is available in a 3 mm × 3 mm, 16-lead LFCSP or 16-lead TSSOP package. The AD5541A is available in a 3 mm × 3 mm, 10-lead LFCSP or 10-lead MSOP package.

Note that the AD5541A does not include the Kelvin sense lines for the reference voltage and ground, the clear function, and the R _FB and R _INV resistors.

Both the AD8657 and ADR421 are available in 8-pin MSOP packages.

Measurement results indicate that the AD5542A/AD5541A are ideal for high-precision, low-noise level setting applications. In this high-precision, high-performance, low-power system, DC performance levels are maintained through the ADR421 reference and the AD8657 reference buffer. Measurements are made directly on VOUT without the optional output buffer connected.

Supply current measurement

The total supply current and the supply current of individual devices are measured using precision ammeters.

The total supply current for this circuit was measured to be 0.97 mA, while the data sheet maximum value was less than 1.5 mA. 

Table 1 lists the measurement results and data sheet values. The overall system power consumption is very low (less than 5 mW), but the accuracy is very high.

Integral nonlinearity and differential nonlinearity measurements

Integral nonlinearity (INL) error refers to the deviation of the actual DAC transfer function from the ideal transfer function, expressed in LSB. Differential nonlinearity (DNL) error is the difference between the actual step size and the ideal value of 1 LSB. This circuit provides 16-bit resolution with ±1 LSB DNL and INL. Figures 3 and 4 show the measured INL and DNL performance, respectively.

Layout and routing considerations

In any circuit where precision is important, power and ground return layout on the circuit board must be carefully considered. The printed circuit board (PCB) containing this circuit should have the analog portion separated from the digital portion. If this circuit contains other devices in the system that require an AGND to DGND connection, the connection can only be made at one point. This ground point should be as close as possible to the AD5542A/AD5541A. This circuit should use a multi-layer PCB with larger area ground and power layers. For more discussion on layout and grounding, please refer to tutorial MT-031 .

The AD5542A/AD5541A power supplies should be bypassed with 10 μF and 0.1 μF capacitors. These capacitors should be as close to the device as possible, preferably directly opposite the device with the 0.1 μF capacitor. The 10 μF capacitor should be a tantalum bead or ceramic type capacitor. The 0.1 μF capacitor must have low equivalent series resistance (ESR) and low equivalent series inductance (ESL), which are typically found in ordinary ceramic capacitors. The 0.1 μF capacitor provides a low-impedance path to ground for high frequencies caused by transient currents caused by internal logic switches. For more information on proper decoupling techniques, please refer to Tutorial MT-101 .

Power traces should be as wide as possible to provide a low impedance path and reduce the effects of glitches on the power lines. Clocks and other fast-switching digital signals should be digitally shielded from other devices on the board.