The circuit shown in Figure 1 is a 10 MHz to 6 GHz wideband active mixer that integrates an interface for direct interfacing to a frequency synthesizer-based low phase noise local oscillator (LO).

This circuit provides an optimal solution and is extremely attractive for broadband applications requiring frequency conversion to higher or lower frequencies. This two-chip circuit covers a wide LO frequency range from 35 MHz to 4400 MHz. The LO interface is simple and seamless in design, eliminating the need for baluns, matching networks, and LO buffers. Additionally, mixer bias adjustment allows IP3, noise figure, and supply current to be optimized based on application requirements or input signal size.

The ADF4351 is a wideband fractional-N and integer-N phase-locked loop PLL frequency synthesizer covering the frequency range from 35 MHz to 4400 MHz. The device features an integrated voltage-controlled oscillator (VCO) with a fundamental frequency range from 2200 MHz to 4400 MHz. Multi-octave operation can be achieved using a set of frequency dividers.

The ADL5801 is a high-linearity, double-balanced, active mixer with an integrated LO buffer amplifier that supports frequencies from 10 MHz to 6000 MHz. The mixer has an offset adjustment feature that optimizes input linearity, noise figure, and DC operating current. The circuit shown in Figure 1 has a simple LO interface and is suitable for applications requiring wideband upconversion or downconversion. The interface covers the RF frequency range from 35 MHz to 4400 MHz.

The ADF4351 PLL has a differential LO output interface, and the ADL5801 is optimized for differential LO driving. The differential interface provides common-mode noise rejection and even-order harmonic cancellation.

Under normal circumstances, it is recommended to use a pull-up bias inductor at the output port of the ADF4351. This solution outputs higher power but limits the frequency range of the device. The standard evaluation board is equipped with two 7.5 nH pull-up inductors for optimal performance above 500 MHz. In the circuit shown in Figure 1, the bias inductor is replaced by two 50 Ω pull-up resistors to reduce the frequency dependence of the output interface. This change results in a reduction in output power; however, the ADL5801 can tolerate this limitation because the device is rated for a LO drive level as low as −10 dBm. Figure 2 compares the output power of the device under two pull-up network conditions: resistive and inductive.

The resistive pull-up network represents a nominal differential impedance of 100 Ω at the output, while the differential input impedance of the ADL5801LO port is 50 Ω. Impedance mismatch in the mixer LO path does not degrade circuit performance. However, it is recommended to keep the length of the connecting traces between devices as short as possible to reduce the impact of impedance mismatch.

The PLL mixer interface described above exhibits excellent wideband performance, as shown in Figures 3 and 4. The circuit maintains input IP3 above 25 dBm at frequencies below 3500 MHz and at 23 dBm at frequencies up to 4400 MHz. According to the circuit performance, the conversion gain exceeds −0.7 dB and the noise figure is less than 12.2 dB in the entire operating frequency band.

The ADF4351 activates several parts of its divider network to produce an output frequency that spans multiple octaves. The power consumption of the circuit depends on the operating frequency and the bias point of the mixer. The combination of these parts determines the power consumption of the PLL. For example, when the PLL is programmed to output a frequency of 35 MHz, the device activates all 6 divider networks and consumes 132 mA. This point represents the worst-case power consumption point of the device. Similarly, the ADL5801's bias level, which can be used to adjust IP3 and noise figure, determines the mixer's power consumption. The VSET pin is used to adjust the bias level of the device. Figures 5 and 6 show the mixer’s DC current, input IP3, and noise figure performance as a function of VSET voltage.