The circuit shown in Figure 1 is a wideband receiver front end based on the ADA4960-1 ultralow noise differential amplifier driver and the AD9434 12-bit, 500 MSPS analog-to-digital converter .

Third-order Butterworth anti-aliasing filters are optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss caused by the filter network, transformer and other resistive components is only 1.2 dB.

The overall circuit bandwidth is 290 MHz and the passband flatness is 1 dB. The measured SNR and SFDR at 140 MHz analog input were 64.1 dBFS and 70.4 dBc, respectively.

This circuit accepts a single-ended input and converts it to a differential signal using a wide bandwidth (3 GHz) M/A-COM ECT1-1-13M 1:1 transformer. The differential input impedance of the 5 GHz ADA4960-1 differential amplifier is 10 kΩ. The gain is adjustable from 0 dB to 18 dB by selecting the external gain setting resistor RG. The differential output impedance is 150 Ω.

The ADA4960-1 is an ideal driver for the AD9434, which enables a fully differential architecture in the ADC via a low-pass filter, providing good high-frequency common-mode rejection while minimizing second-order distortion products. The ADA4960-1 provides a gain of 0 dB to 18 dB depending on the external gain resistor. In this circuit, a 3.4 dB gain is used to compensate for the insertion loss of the filter network (1.1 dB) and transformer (0.1 dB), providing a total signal gain of 2.3 dB. An input signal of approximately 5.4 dBm produces a full-scale 1.5 V pp differential signal at the ADC input.

The anti-aliasing filter is a third-order Butterworth filter designed using standard filter design procedures. The Butterworth filter was chosen because it has a flat response within the passband. Third-order filters produce an AC noise-to-bandwidth ratio of 1.05 and can be designed with the help of several free filter programs, such as Nuhertz Technologies Filter Free (hwww.nuhertz/filter) or Quite Universal Circuit Simulator (Qucs) Free Simulation (www.qucs. sourceforge.net) .

For best performance, the ADA4960-1 should be loaded with a net differential load of 100 Ω. The 5 Ω series resistor isolates the filter capacitor from the amplifier output, and the 62 Ω resistor is in parallel with the downstream impedance, resulting in a net load impedance of 101 Ω when the 10 Ω series resistor is added.

A 5 Ω resistor in series with the ADC input isolates internal switching transients from the filter and amplifier. The 511 Ω resistor is placed in parallel with the ADC to lower the input impedance of the ADC, making performance more predictable.

The third-order Butterworth filter is designed with a source impedance of 70 Ω, a load impedance of 338 Ω, and a 3 dB bandwidth of 360 MHz. The values ​​calculated by the program are shown in Figure 2.

The values ​​chosen for the filter passive components are the closest standard values ​​to the program-generated values.

Subtract the ADC's internal 1.3 pF capacitance from the second shunt capacitance value (10.01 pF) to obtain a value of 8.71 pF. In this circuit, this capacitor is implemented using two 18 pF capacitors to ground, as shown in Figure 1. This can not only provide the same filtering effect, but also obtain a certain AC common mode suppression.

Filter and interface design program

To achieve optimal performance (bandwidth, SNR, SFDR, etc.), the amplifier and ADC should impose certain design constraints on the general circuit:

1. Amplifiers should refer to the correct DC loading recommended by the data sheet for optimal performance.
2. The correct number of series resistors must be used between the amplifier and filter loads. This is to prevent unwanted peaks within the passband.
3. The input to the ADC should be reduced with an external shunt resistor and the correct series resistor used to isolate the ADC from the filter. This series resistor also reduces peaking.

The general circuit shown in Figure 5 is applicable to most high-speed differential amplifier/ADC interfaces and will serve as the basis for this article's discussion. This design approach tends to take advantage of the relatively high input impedance of most high-speed ADCs and the relatively low impedance of the driving source (amplifier) ​​to minimize the insertion loss of the filter.

The basic design process is as follows:

1. Select the external ADC termination resistor RTADC so that the parallel combination of RTADC and RADC is between 200 Ω and 400 Ω
2. Choose RKB based on experience and/or ADC data sheet recommendations, typically between 5 Ω and 36 Ω.
3. Calculate the filter load impedance using the following equation:
   

   ZAAFL = RTADC || (RADC + 2RKB)

4. S selects the amplifier external series resistor RA. If the amplifier differential output impedance is in the 100 Ω to 200 Ω range, RA should be less than 10 Ω. If the amplifier output impedance is 12 Ω or less, RA should be between 5 Ω and 36 Ω.
5. Choose RTAMP so that the total load ZAL obtained by the amplifier is best suited for the specific differential amplifier selected by the following formula:
   

   ZAL = 2RA + (ZAAFL || 2RTAMP)

6. Calculate filter source impedance
   

   ZAAFS = 2RTAMP || (ZO + 2RA)

7. Use a filter design program or table to design a filter using source impedance, load impedance, ZAAFS and ZAAFL, filter type, bandwidth, order, etc. The bandwidth is approximately 40% greater than half the sample rate to ensure flatness from dc to fs/2.
8. The internal ADC capacitance CADC should be subtracted from the final shunt capacitance value generated by the program. The program will give the differential shunt capacitor value CSHUNT2. The final common mode shunt capacitor is:

After the above preliminary calculations, the following items of the circuit should be understood.

1. The CAAF2 value should be at least 10 pF, several times greater than CADC. This minimizes the filter's sensitivity to CADC fluctuations.
2. The ratio of ZAAFL to ZAAFS should not be higher than about 7 to bring the filter within the limits of most filter tables and design programs
3. The CAAF1 value should be at least 5 pF to minimize sensitivity to parasitic capacitance and component fluctuations.
4. The inductance LAAF should be a reasonable value, at least a few nH.

In some cases, filter design programs can provide more than one unique solution, especially for higher order filters. Always choose the solution with the most reasonable combination of component values. Also choose a configuration that ends with the shunt capacitor so that the shunt capacitor combines with the ADC input capacitance.

Circuit Optimization Techniques and Tradeoffs

The parameters within this interface circuit are highly interactive; therefore optimizing all critical specifications of the circuit (bandwidth, bandwidth flatness, SNR, SFDR, gain, etc.) is nearly impossible. However, by changing RA and RKB, the spikes that typically occur within the bandwidth response can be minimized.

The spikes within the passband decrease as the value of the output series resistor RA increases. However, as this resistor value increases, the signal attenuation also increases and the amplifier must drive a larger signal to fill the full-scale input range of the ADC.

RA value also affects SNR performance. Larger values ​​tend to slightly increase SNR while reducing bandwidth peaking because higher signal levels are required to drive the ADC full scale.

The RKB series resistor at the ADC input should be chosen to minimize distortion caused by any residual charge injection (from the ADC's internal sampling capacitance). Increasing this resistance also tends to reduce in-band spikes.

However, increasing RKB increases signal attenuation, so the amplifier must drive a larger signal to fill the ADC's input range.

Another way to optimize passband flatness is to slightly change the filter shunt capacitor CAAF2.

The ADC input termination resistor, RTADC, should generally be selected so that the net ADC input impedance is between 200 Ω and 400 Ω. Lowering this resistor reduces the effect of the ADC input capacitance and stabilizes the filter design, but it increases the circuit's insertion loss. Increasing this value will also reduce peaks.

The trade-offs between the above factors can be somewhat difficult. In this design, each parameter is equally weighted; therefore, the values ​​selected represent the interface performance for all design features. In some designs, different values ​​can be selected to optimize SFDR, SNR, or input drive levels based on system requirements.

Note that the signal in this design is ac-coupled with a 0.1 μF capacitor to block the common-mode voltage between the amplifier, its termination resistor, and the ADC input. See the AD9434 data sheet for details on common-mode voltages.

Passive Components and PCB Parasitic Considerations

The performance of this or any high-speed circuit is highly dependent on proper PCB layout, including but not limited to power supply bypassing, controlled impedance lines (if required), component placement, signal routing, and power and ground planes. See Tutorial MT-031 and Tutorial MT-101 for details on high-speed ADC and amplifier PCB layout .

Low parasitic surface mount capacitors, inductors and resistors are used as passive components within the filter. The inductor chosen is from the Coilcraft 0603CS series. The stability and accuracy of the surface mount capacitors used in the filter are 5%, C0G, type 0402.

Complete documentation for the system is available in the CN-0238 Design Support Package ( www.analog.com/CN0238-DesignSupport ).