This low-power mode scheme achieves processor power consumption of less than 0.1 mW while maintaining LPDDR2 memory power consumption in the self-refresh state at approximately 1.6 mW. The system solution consists of AM437x Sitara processor, LPDDR2 memory and TPS65218 power management IC, and has been optimized for new low-power modes while supporting traditional low-power modes. Minimize processor power by turning off all processor power except the RTC power. System power state transitions, including power control, can be performed by a single interface signal (PMIC_PWR_EN signal) using PMIC register programming.
Blockdiagram
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