A development board using 32G0 and domestic FPGA
32 communicates with FPGA via SPI
G0 uses the internal HSE to generate the clock. At the same time, the G0 internal PLL outputs a high-speed clock to the FPGA as a clock (up to 16M). You can also use the FPGA internal PLL to generate the clock (the FPGA PLL is a bit weird, I am too lazy to study it).
FPGA and 32 share a RST button, and 32 and FPGA each have an independent LED and a button.
How to use AG1280 can be found in libc boss’s AG1280Q48 minimum system board V1
You can refer to the schematic diagram for the rest.
The attachment provides test project files for STM32G0 and FPGA. FPGA provides quartus project and comprehensive project, and STM provides CUBEIDE project based on LL library.
If there is no problem with the board, you can see that IO16 outputs a 2Mhz clock.
BOM connector go to Xxin Electronics to buy similar products by yourself
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