All onboard USB3.0 lines have been successfully verified and can be run.
There are three routes in total:
1: A male>A female
2: C female > A female (use VL160 as a double-sided switching chip)
3: Mother B > Mother A
The line width and line spacing on the board can be used as a reference.
The process used for verification is: JLC2312, lamination, there is no sequence requirement for the inner layer, the thickness is 1mm (only 1mm can use the splint C port in lane2)
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It is your responsibility to test the circuit yourself and determine its suitability for you. EEWorld will not be liable for direct, indirect, special, incidental, consequential or punitive damages arising from any cause or anything connected to any reference design used.
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