IAP15F2K61S2 LQFP44 to DIP40

IAP15F2K61S2 LQFP44 to DIP40 Adapter Board
Version Notes - 2024.7.7
1. Added external crystal oscillator selection pins P1.6 and P1.7.
2. Added external reset selection pin P54.
3. DIP40 pins 29, 30, and 31 are left floating; jumpers can be soldered later if needed.
4. The pin definitions are the same for STC15F/STC15W series LQFP44 packages and should also be applicable.
5. V1 is my first board design with absolutely no prior experience; it features automatic routing, no copper plating, and is already fabricated.
6. V2 is a modified version of V1, optimized after watching EDA video tutorials; DRC checked and found no errors; no copper plating; not yet fabricated.
7. I only have a junior high school education, and my work has nothing to do with electronics; I designed this out of hobby in my spare time, hoping it will be helpful to others. Please correct any shortcomings yourself.
Version V1 is already fabricated, tested and downloadable; all I/O LEDs are working.
Detecting target microcontroller...
Microcontroller model: IAP15F2K61S2
Software protocol: 7.2.5S
Current chip hardware options are:
. After the next cold boot, the system clock source is the internal IRC oscillator
. Current oscillator frequency: 22.078MHz
. . Oscillator amplification gain enabled
. . Power-down wake-up timer frequency: 34.525KHz
. . P3.2 and P3.3 are irrelevant to the next download
. . No additional reset delay is added during power-on reset
. . The reset pin remains the reset pin
. . Reset upon low voltage detection
. . Low voltage detection threshold voltage: 3.82V
. . EEPROM operations cannot be performed under low voltage
. . The internal watchdog timer is not activated during power-on reset. .
The prescaler for automatically activating the internal watchdog timer upon power-on is: 256.
. The watchdog timer stops counting in idle state
. . After the watchdog timer is activated, the software can modify the prescaler, but cannot disable the watchdog timer
. The user EEPROM area will not be erased during the next user program download
. There is no related 485 port control during the next user program download
. The download password does not need to be verified during the next download
. TXD and RXD are independent I/O pins
. After chip reset, the TXD pin is a weak pull-up bidirectional port
. After chip reset, P2.0 outputs a low level
. Internal reference voltage: 1239 mV (reference range: 1150~1320mV).
Microcontroller model: IAP15F2K61S2.
Software protocol: 7.2.5S.