Hirmr

JX-12F Development Board - Intelligent Mechanism

 
Overview
1. Module Description:
The JX-12F is a wireless module based on a WiFi+BLE single-chip SoC as the main controller. It can meet the development needs of low-power and high-performance IoT applications. The core processor JX-1001 of this module integrates 2.4G Wi-Fi (802.11b/g/n) and BLE5.0 baseband and MAC design. Its microcontroller subsystem includes a low-power 32-bit RISC CPU, cache, and memory. It has an advanced power management unit that supports multiple low-power modes. Peripheral interfaces include UART, GPIO, ADC, DAC, PWM, I2C, SDIO, SPI, IR remote, etc.
2. Physical Image:
All pins are brought out. The board has an onboard CH340, and the serial port has bidirectional ESD protection against electrostatic discharge and rapid overvoltage. Silkscreen instructions: 240202 represents the date February 2nd, 2024; PDSU represents Pingdingshan University; JX-12F represents the module name;
3. Download tutorial
: Use a Type-C port to download. The board has a CH340 chip with a BOOT DIP switch: X: Download, Y: Run.
See the operation package below for detailed instructions. I'll update this later.
参考设计图片
×
 
 
Search Datasheet?

Supported by EEWorld Datasheet

Forum More
Update:2026-03-26 15:48:50

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
community

Robot
development
community

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号