16-bit, single-supply, buffered voltage output analog-to-digital converter with less than ±1 LSB integral and differential nonlinearity
By interleaving Renesas' low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs. This reference design demonstrates the performance attainable by combining Renesas' ADC technology and SP Devices' interleaving algorithms. In this design, four ISLA112P50 12-bit, 500MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.