Circuit functions and advantages

The circuit shown in Figure 1 is a complete single-supply 16-bit buffered voltage output DAC that utilizes a CMOS DAC and an innovative amplifier with no crossover distortion to maintain integral and differential nonlinearity errors to ±1 LSB.

Most rail-to-rail op amps have crossover nonlinearity errors, which can be as high as 4 to 5 LSB in a 16-bit system. This circuit eliminates this error.

This industry-leading solution is ideal for industrial process control and instrumentation applications that require a compact, single-supply, low-cost, high-linearity 16-bit buffered voltage source.

When operating from a single 6 V supply, the total power consumption of the three active devices is typically less than 25 mW.

Circuit description

Figure 1 shows the single-supply signal chain consisting of a reference, a digital-to-analog converter (DAC), and a DAC buffer. The DAC's reference voltage is equal to the supply voltage V _DD to maximize dynamic output range and signal-to-noise ratio. This configuration requires a rail-to-rail input and output buffer amplifier.

The DAC is the AD5541A , which is a 16-bit, serial input, voltage output, segmented R/2R CMOS DAC. The output voltage of the DAC is related to the reference voltage, as shown in the following equation:

_{Thus, V OUT} is 2.5 V at midscale _and 5 V at full scale

The LSB size is 5 V/65,536 = 76.3 μV.

At 16 bits, 1 LSB is also equivalent to 0.0015% of full scale, or 15 ppm FS.

The ADR4550 uses an innovative core topology to achieve high accuracy while delivering industry-leading temperature stability and noise performance. The ADR4550 voltage reference provides a highly accurate, low-noise (2.8 μV pp, 0.1 Hz to 10 Hz), and stable voltage reference for the DAC. The low output voltage temperature coefficient (2 ppm/°C maximum) and low long-term output voltage drift also improve system accuracy over lifetime and temperature.

The ADR4550B has room temperature initial accuracy of ±0.02% (max), which is equivalent to approximately 14 LSB at 16 bits. This initial error can be eliminated through system calibration. The reference drives the DAC's REF pin and powers the DAC and output buffer. Therefore, it must provide a maximum load current of 3.9 mA. The ADR4550 is capable of driving up to 10 mA with 25 ppm/mA load current regulation.

The ADR4550 reference voltage source is placed as close as possible to the REF pin of the DAC to minimize the length of the output trace and thus minimize the error caused by voltage drop. The current flowing through the PCB traces will produce an IR voltage drop. When the traces are long, this voltage drop may reach several millivolts or more, causing considerable errors. A 1-ounce copper trace 1 inch long and 0.005 inch wide has a resistance of approximately 100 m¬ at room temperature. With a load current of 10 mA, this trace can cause an error of 1 mV.

The output buffer is ADA4500-2 . The device is a high-precision amplifier with a maximum offset voltage of 120 V, offset drift of less than 5.5 V/°C, 0.1 Hz to 10 Hz noise of 2 V pp, and a maximum input bias current of 2 pA. Its important features are rail-to-rail input and output swing and zero-crossover distortion, making it suitable for use as a DAC buffer.

For the detailed working principle of ADA4500-2, please refer to the ADA4500-2 data sheet. A typical rail-to-rail input amplifier uses two differential pairs to achieve rail-to-rail input swing (see MT-035 guide ). One differential pair is active in the upper part of the input common-mode voltage range and the other differential pair is active in the lower part of this range. This classic dual differential pair topology produces crossover distortion when one differential pair is connected to another differential pair. When this amplifier is used as a DAC buffer, changes in offset voltage can cause nonlinear errors. The ADA4500-2 utilizes an integrated charge pump in its input structure to achieve rail-to-rail input swing, eliminating the need for a second differential pair. Therefore, it has no crossover distortion. Using a zero-crossover distortion amplifier in this single-supply system not only maintains high linearity over the input common-mode/input digital code range, but also provides a wide dynamic output range.

The DAC's output impedance is constant (typically 6.25 k¬) regardless of the output code. However, the output buffer should have high input impedance (low input bias current) to minimize errors. The ADA4500-2 is a suitable device with high input impedance and a maximum input bias current of 2 pA at room temperature and 190 pA maximum over temperature. The worst-case error due to input bias current is 1.2 V, which is much less than 1 LSB.

The AD5541A is available in a 10-lead MSOP or 10-lead LFCSP package. The ADR4550 is available in an 8-pin SOIC package, and the ADA4500-2 is available in an 8-pin MSOP or 8-pin LFCSP package.

Measurement results show that the combination of the AD5541A, ADR4550, and ADA4500-2 is an excellent solution for high-precision, low-noise applications. The ADA4500-2 has no crossover distortion and maintains DAC linearity.

Integral nonlinearity (INL) and differential nonlinearity (DNL) measurements

Integral nonlinearity (INL) error refers to the deviation of the actual DAC transfer function from the ideal transfer function, expressed in LSB. Differential nonlinearity (DNL) error is the difference between the actual step size and the ideal value of 1 LSB. This system solution provides 16-bit resolution with ±1 LSB DNL and INL. Figures 2 and 3 show the DNL and INL performance of this circuit.

Note that the DNL and INL measurements exclude 200 codes (approximately 15 mV) starting at either end of the range. This is because the rail-to-rail output stage becomes nonlinear in this interval, as described in Tutorial MT-035.

Figure 4 shows the nonlinear error caused by using an op amp with a conventional rail-to-rail input stage. Note that when the common-mode voltage differs by approximately 1.7 V from the +5 V supply rail, a peak error of approximately 4 LSB occurs.

Board Layout Considerations

Power and ground return layout on the circuit board should be carefully considered. The printed circuit board should separate the analog part from the digital part. If the circuit is in a system with multiple devices that require an analog ground to digital ground connection, the connection can only be made at one point. Power supplies to all devices should be bypassed with a capacitor of at least 0.1uF. These bypass capacitors should be as close to the device as possible, preferably directly opposite the device. The 0.1 ¬F capacitor selected should have low effective series resistance (ESR) and low effective series inductance (ESL), such as ceramic capacitors. The 0.1¬F capacitor provides a low-impedance path to ground for transient currents. Power traces should be as wide as possible to provide a low impedance power path. For optimal performance, proper layout, grounding, and decoupling techniques must be used (refer to Tutorial MT-031, "Grounding Data Converters and Unraveling the Mysteries of AGND and DGND" and Tutorial MT-101 - "Decoupling Technology")