Understanding and Managing Buck Regulator Output Ripple

1 Introduction

In our new power supply design , capacitors and inductors need to be placed in half of the space, which results in our PCB design layout being very large.

But if we choose the smallest point-of-load regulator and use the most cost-effective passive components, we generate the most compact layout and reduce the PCB area. But then we check to see the critical output ripple and find that the ripple exceeds our expectations . What causes this ?

2. Analyze the causes of DCDC ripple

Let's first understand what constitutes the output ripple of a step-down DC/DC regulator. It is a composite waveform.

Traditionally only three main elements shown in Figure 1 have been considered:

( 1 ) Triangular wave generated by applying an inductor current ramp across the equivalent series resistance (ESR) of the output capacitor . A 22 µF X5R ceramic capacitor may have an ESR of only 2 mΩ. Considering an inductor peak-to-peak current ripple of 1 A, the ESR ripple is 2 mV (less if you use multiple capacitors in parallel).

( 2 ) Pseudo-sinusoidal component due to output capacitance. For the same output capacitor and ripple current as in the above points, the capacitor ripple will be about 8 mV (less for multiple output capacitors in parallel).

( 3 ) The square component generated at both ends of the equivalent series inductance (ESL) of the output capacitor . For a 22 µF X5R capacitor, the ESL is approximately 0.5 nH, resulting in a ripple of approximately 2 mV.

Figure 1: Typical output ripple waveform

However, what we measured has spikes at the edges, and when you invert the inductor shown in Figure 2, the square wave content changes polarity:

Figure 2: Measured output ripple

What causes these bad ingredients? More importantly, what can you do?

3. Peak of ripple

When we choose the inductor, the self-resonant frequency (SRF) is higher than your regulator switching frequency, so everything is fine. Let's revisit this - an inductor has SRF because it has parallel parasitic capacitance. Applying a fast edge of the switching voltage to the parasitic capacitance creates a large current spike through the capacitor, which in turn creates a large voltage spike across the ESL of the output capacitor (see Equation 1):

       (1)

To reduce this peak:

( 1 ) Choose an inductor with smaller parasitic capacitance. Find the highest SRF value for the inductor and rating you need . Lower inductors tend to have lower parasitic capacitance (as do lower current ratings), so don't overspecify the inductance or current rating.

( 2 ) Reduce the output capacitor ESL. Select the smallest capacitor package size that meets your output capacitance requirements. Using multiple smaller capacitors in parallel means that the package size (and therefore ESL) of each capacitor can be smaller, while paralleling inductors also reduces the overall ESL.

( 3 ) Reduce the transient voltage (dV/dt) of the switching node (increase the t value). Some regulators may allow direct control of the switch node edge, but more often than not you can put a small resistor in series with the bootstrap capacitor to slow down the edge. This affects efficiency, so the first two options are preferable.

4. Square wave

Suppose we choose a cost-effective unshielded inductor. Magnetic fields from unshielded (or resin-shielded inductors) can spread beyond the physical body of the component. The simulation plots in Figure 3 show the magnetic fields for an unshielded open drum inductor and a fully shielded molded inductor. 

Figure 3: Magnetic field from unshielded drum and shielded molded inductor (Source: Courtesy of Coilcraft)

This compact layout places the output capacitor next to the inductor. The escaping magnetic field couples to the ESL of the capacitor (and to a lesser extent the output rail loop) and generates a square wave component. When the inductor reverses direction, the current and magnetic field in the inductor reverse direction (like the points in an exchange-coupled inductor), so the square wave component reverses direction.

To reduce this effect:

( 1 )  Choose a shielded inductor to reduce the leakage flux that produces this coupling. If you are using an unshielded or semi-shielded inductor, choosing an inductor with larger xy dimensions but a smaller profile will reduce the air gap height and thus reduce the fringing flux.

( 2 )  Reduce the output capacitance ESL as described above.

( 3 )  Do not place the output capacitor and trace directly next to the inductor, where the magnetic field is highest. In situations where space is critical, consider placing the inductor on the other side of the board, in a clamshell configuration opposite the rest of the regulator circuit. This places the output capacitor away from the plane of the inductor where the magnetic field is strongest.

Now we can view the output ripple waveform and take apart the different components. By choosing the right external passive components and making some careful layout decisions, we can still achieve a tiny, cost-effective solution and optimize the output ripple for the application .