High-Side FET Load Switch Primer (1)

    High-side load switches and their operation remain a popular choice for many engineers and designers of battery-powered portable devices such as feature-rich cell phones, mobile GPS devices, and consumer entertainment gadgets. This article takes an easy-to-understand, non-mathematical approach to explaining various aspects of MOSFET-based high-side load switches and discusses the various parameters that must be considered throughout the design and selection process.

    What is high-end

    The definition of a load switch is that it is controlled by an external enable signal and connects or disconnects a power source (battery or adapter) to a given load. Compared to a low-side load switch, a high-side switch sources current to the load, while a low-side switch connects or disconnects the load to ground, thereby sinking current from the load.

    A high-side load switch is different from a high-side power switch. A high-side power switch manages output power and therefore typically limits its output current. In contrast, a high-side load switch passes the input voltage and current to the load and therefore does not include current limiting.

    A high-side load switch consists of three components:

    1. The pass element, essentially a transistor, typically an enhancement-mode MOSFET. The pass element operates in the linear region to transfer current from the source to the load, acting like a switch (as opposed to an amplifier).

    2. The gate control block, which provides voltage to the gate of the pass element to turn it on or off. Also known as the level shifter, this block shifts the external enable signal to generate a gate voltage (bias) high enough or low enough to fully turn the pass element on and off.

    3. Input logic blocks, whose main function is to interpret the enable signal and trigger the gating blocks to open and close the path elements.

    Passage components

    The pass element is the most fundamental part of a high-side switch. The most commonly viewed parameters, especially the on-state resistance (R DSON ), are directly related to the structure and characteristics of the pass element.

    Because enhancement-mode MOSFETs typically consume less current during operation, leak less current during shutdown, and offer greater thermal stability than bipolar transistors, they are more widely used as pass elements in high-side load switches. Therefore, this article will focus exclusively on pass elements based on enhancement-mode MOSFETs.

    The enhancement-mode MOSFET pass element can be either an N-channel or a P-channel FET.

    When the gate voltage (VG) of an N-channel FET is higher than its source voltage (VS) and drain voltage (VD) by a threshold value (VT), the N-channel FET is fully turned on or in its linear region. The following formula gives the mathematical representation of the ON condition:

    V G – V S = V GS > V T

    V G – V T > V D或 V GS – V T > V DS

    Where VG is the gate voltage; VS is the source voltage; VD is the drain voltage; VT is the FET's threshold voltage; VGS is the voltage drop from gate to source; and VDS is the voltage drop from drain to source. (All signs represent positive numbers.)

    When the N-channel FET is turned on, the drain current ID is positive and flows from the drain to the source, as shown in Figures 1 and 2.

    Figure 1: N-channel FET high-side load switch with internal charge pump.

    Figure 2: N-channel FET high-side load switch with external V BIAS input.

    A P-channel FET is fully on or in its linear region when its gate voltage (VG ) is below its source voltage (VS ) and drain voltage (VD ) threshold (VT ):

    V S – V G = V SG > V T

    VD – VT > VG or V SG – VT > V SD

    Where VG is the gate voltage; VS is the source voltage; VD is the drain voltage; VT is the FET's threshold voltage; VSG is the voltage drop from source to gate; and VSD is the voltage drop from source to drain. (Again, all signs represent positive numbers.)

    When the P-channel FET is on, the drain current ID is “negative” and flows from source to drain, Figure 3.

    Figure 3: P-channel FET high-side load switch.

    N-channel FETs use electrons as majority carriers, which have a higher mobility than holes, the majority carriers in P-channel FETs. This means that, given the same physical dimensions, N-channel FETs have higher transconductance than P-channel FETs, which translates to lower drain-to-source resistance during the on-state, or R DSON .

    Typically, N-channel FETs have an R DSON that is 2 to 3 times lower than similarly sized P-channel FETs, and therefore have an ID that is higher by a similar factor (not considering other constraints such as bond wire thickness and packaging). This also means that for the same R DSON and ID, N-channel FETs typically require less silicon and therefore have lower gate capacitance and threshold voltage than P-channel FETs.

    Furthermore, because the VD of an N-channel FET remains below VG by a factor of VT when the switch is on, and VD is typically tied to VIN, a very low VIN is delivered to the load. Theoretically, the VIN of an N-channel FET switch can be as low as near ground (GND) or as high as VG – VT. On the other hand, a P-channel FET switch delivers a VIN (tied to VS) that is always higher than VG + VT to the load.

    However, this does not mean that N-channel FETs are always better than P-channel FETs as pass elements.

    As mentioned previously, a fundamental characteristic of N-channel FETs is that for the switch to operate in its linear region when on, VG needs to be a value V higher than VD. However, since VD is almost always connected to VIN, which is typically the highest voltage seen by the switch, VG must be either sourced from an existing voltage (such as an external enable signal (EN)) or "biased" with a DC offset, a separate new high-voltage rail often called VBIAS.

    If the gate voltage is shifted up from the EN level, additional internal circuitry is required, typically a charge pump. The charge pump requires an internal oscillator and at least one "flying" capacitor on the chip to generate the gate voltage, which is typically a multiple of the EN value during the on-time period. This, of course, increases design complexity and silicon, which offsets the silicon savings gained by the lower R DSON characteristic of N-channel FETs. In fact, when load currents are relatively low (up to a few amperes), the added silicon area of ​​the charge pump outweighs the reduction in R DSON factor, making N-channel switches a more expensive and complex solution. For a P-channel alternative, see Figure 1 for more details.

    If the gate voltage is biased by a DC offset, V BIAS , then the increase in silicon area is not significant, as a charge pump is no longer required. However, this may not be the best solution from a system perspective, as it may not have an ultra-high voltage rail, as is the case with most battery-powered devices and equipment (see Figure 2).

    However, in the case of a P-channel FET, VG is always lower than VS (relative to VIN). As long as VS remains near the VG value of VT when the switch is on, it always operates in the linear region, without the need for special internal circuitry or external voltage rails. This is achieved by using a gate control block to "level shift" EN to the correct VG level. This option does not require much circuit implementation or additional silicon area, as shown in Figure 3.

    Typically, N-channel high-side load switches are a good choice in high-power systems requiring extremely low R DSON or in low-input voltage systems that need to pass V IN close to GND to the load. On the other hand, P-channel high-side load switches offer advantages in low-power systems requiring design simplicity or in high-input voltage systems that need to pass high V IN to the load. See Table 1 for a summary of key parameters for typical N-channel and P-channel FET-based switches.

    Table 1: Comparison of switches based on N-channel FETs and P-channel FETs.