Improving Power Reliability Using High-Voltage GaN Devices

Gallium nitride (GaN) high electron mobility transistors (HEMTs) improve converter efficiency and have lower gate charge, lower output charge, and lower on-resistance than silicon FETs with the same voltage rating. In high-voltage DC/DC converter applications with bus voltages greater than 380V, depletion-mode (d-mode) GaN HEMTs are more popular than enhancement-mode (e-mode) GaN HEMTs.

This is because the gate voltage range of d-mode GaN HEMTs is much wider than that of e-mode GaN HEMTs. However, d-mode GaN HEMTs have a "normally on" characteristic, which is not ideal for common switch-mode power supply applications. Two commercial high-voltage GaN devices (shown in Figure 1) use d-mode GaN HEMTs with different configurations to form "normally off" devices.

Figure 1: High-voltage GaN device using synchronous drive technology (a); and direct drive technology (b)

Both GaN devices have a high-voltage GaN HEMT in series with a low-voltage silicon FET, but with different driving schemes. The high-voltage GaN device with synchronous driving technology shorts its high-voltage GaN HEMT gate pin with the source pin of its low-voltage silicon FET. By turning on the low-voltage silicon FET, we can control the on/off of the entire device.

There are three possible states for synchronously driving high voltage GaN devices:

    ·  Forward blocking . When V  DS,device  > 0 and V  GS,LV_Si  <  V  GS(th),LV_Si , the high-voltage GaN HEMT can be turned on or off, depending on whether V  DS,device is higher than the high-voltage GaN HEMT  V  GS threshold voltage (  V  GS(th),HV_GaN  ). Note that V  GS(th),LV_Si is the V  GS threshold voltage of the low-voltage silicon FET . Since V  GS,LV_Si  <  V  GS(th),LV_Si , the low-voltage silicon FET is in the off state and does not conduct any current. If V  DS,device < |  V  GS(th),HV_GaN  |, the high-voltage GaN HEMT remains in the on state and the low-voltage silicon FET maintains the V  DS stress of the entire device. If V  DS,device  ≥ |  V  GS(th),HV_GaN  |, the high-voltage GaN HEMT is turned off, and the V  DS voltage of the high-voltage GaN HEMT is maintained at V  DS,device  +  V  GS(th),HV_GaN , where V  GS(th) ,HV_GaN  < 0.

    ·  Forward conduction . When V  DS,device  > 0 and V  GS,LV_Si  ≥  V  GS(th),LV_Si , the low-voltage Si FET turns on. Regardless of whether the high-voltage GaN HEMT was off or on before entering the forward conduction state, the turn-on of the low-voltage Si FET forces V  GS,HV_GaN  ≈ 0 and turns on the high-voltage GaN HEMT.

    ·  Reverse conduction . When V  DS,device  < 0 and V  GS,LV_Si  <  V  GS(th),LV_Si  ,  V  GS,HV_GaN will clamp to the low voltage silicon FET body diode forward voltage. Therefore, the current will flow through the low voltage silicon FET body diode and the high voltage GaN HEMT. When V  DS,device  < 0 and V  GS,LV_Si  ≥  V  GS(th),LV_Si , the low voltage silicon FET is turned on and V  GS,HV_GaN is forced to zero. Therefore, the current flows through the drain-source channel of the low voltage silicon FET and the high voltage GaN HEMT.

Unlike synchronously driven high-voltage GaN devices, directly driven high-voltage GaN devices only turn on the low-voltage silicon FET once after its VDD voltage is above the undervoltage lockout. We can analyze the device operation in these two cases : 

    ·  If there is no V  DD applied . When V  DD has not been applied to the device  after applying positive V  DS, device , V  GS,HV_GaN remains at zero voltage and the V  DS of the low voltage silicon FET begins to increase. When the V  DS voltage increases to V  GS(th),HV_GaN , the high voltage GaN HEMT will turn off and maintain the voltage of V  DS,device  +  V  GS(th),HV_GaN . This operation is similar to the forward blocking state of the synchronously driven high voltage GaN device.

    With  V  DD applied . After the device is powered up by applying V DD  , the gate driver can generate a negative voltage to directly turn off the high-voltage GaN HEMT. Once the gate driver controls the high-voltage GaN HEMT, the low-voltage silicon FET can continue to conduct until V  DD is removed or any fault is detected.

Using different driving techniques, synchronously driven high-voltage GaN devices and directly driven high-voltage GaN devices have very different characteristics. Synchronously driven high-voltage GaN devices can be used as a direct replacement for silicon FETs. However, the low-voltage silicon FET switches synchronously with the high-voltage GaN HEMT. That is, the body diode of the low-voltage FET can conduct current in steady-state operation. Therefore, the low-voltage silicon FET reverse recovery charge (  Qrr  ) will introduce additional losses and limit  the switching frequency achievable with synchronously driven high-voltage GaN devices.

Compared with synchronously driving high-voltage GaN devices, the low-voltage silicon FET in the directly driven high-voltage GaN device only switches from off to on once and remains on in the steady state. This eliminates the reverse recovery effect caused by the body diode of the low-voltage silicon FET. In addition, the integration of the gate driver and startup logic increases the reliability of the entire power supply.

    TI’s 600V LMG3410 GaN device uses direct drive technology to achieve zero Qrr and  lower gate charge. Over-temperature protection (OTP) and over-current protection (OCP) with fast 50nS fault trigger time are also built in. Using TI’s direct-drive GaN devices in power supplies with totem-pole switching configurations—like totem-pole power factor correction circuits or inductor-inductor-capacitor (LLC) series resonant half-bridge converters—can eliminate concerns about shoot-through and incorrect dead-time settings.

Figure 2 shows a shoot-through test of an LLC series resonant half-bridge converter using the TI LMG3410 as the input switch. During the test, the high-side switch is forced on and the low-side switch is controlled by a drive signal with a gradually increasing duty cycle. Once the OCP trips, the LMG3410 quickly disables its internal driver to turn off the switch. This prevents catastrophic failure of the device.

Figure 2: TI LMG3410 pass-through test of LLC series resonant half-bridge converter: C1 = low-side switch drive signal, CH2 = switch node voltage, CH3 = high-side switch drive signal, CH4 = primary inductor current

We also tested the LMG3410 OTP on the same LLC series resonant half-bridge board with an incorrect dead time setting to force the converter into hard switching operation. You can watch the OTP test video.

By building OCP and OTP into this zero- Q  rr  GaN device, we have solved the most concerning issues in totem-pole switching.