GS820E32Q-138 datasheet, PDF - EEWORLD Datasheet

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GS820E32Q-138: Description2M Synchronous Burst SRAM; File Size239KB，23 Pages; ManufacturerETC

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GS820E32Q-138 Overview

2M Synchronous Burst SRAM

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GS820E32T/Q-150/138/133/117/100/66

TQFP, QFP

Commercial Temp

Industrial Temp

Features

• FT pin for user configurable flow through or pipelined operation.

• Dual Cycle Deselect (DCD) Operation.

• 3.3V +10%/-5% Core power supply

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

• Default to Interleaved Pipelined Mode.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• JEDEC standard 100-lead TQFP or QFP package.

-150

Pipeline tCycle 6.6ns

3-1-1-1 t

3.8ns

270mA

Flow tCycle 10.5ns

Through t

9ns

2-1-1-1 I

170mA

-138

-133

-117

-100

-66

7.25ns 7.5ns 8.5ns 10ns 12.5ns

4ns

4.5

5ns

6ns

245mA 240mA 210mA 180mA 150mA

15ns 15ns 15ns 15ns 20ns

9.7ns 10ns 11ns 12ns 18ns

120mA 120mA 120mA 120mA 95mA

64K x 32

2M Synchronous Burst SRAM

Flow Through / Pipeline Reads

150Mhz - 66Mhz

9ns - 18ns

3.3V VDD

3.3V & 2.5V I/O

The function of the Data Output register can be controlled by the user

via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-

BGA). Holding the FT mode pin/bump low, places the RAM in Flow

through mode, causing output data to bypass the Data Output

activating the rising edge triggered Data Output Register.

DCD Pipelined Reads

The GS820E32 is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are also

available. DCD SRAMs pipeline disable commands to the same

degree as read commands. DCD RAMs hold the deselect command

for one full cycle and then begin turning off their outputs just after the

second rising edge of clock.

Byte Write and Global Write

Byte write operation is performed by using byte write enable (BW)

input combined with one or more individual byte write signals (Bx). In

addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Functional Description

Applications

The GS820E32 is a 2,097,152 bit high performance synchronous

SRAM with a 2 bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPU’s, the device now finds application in synchronous

SRAM applications ranging from DSP main store to networking chip

set support.

Core and Interface Voltages

The GS820E32 operates on a 3.3V power supply and all inputs/

outputs are 3.3V and 2.5V compatible. Separate output power (V

DDQ

)

pins are used to de-couple output noise from the internal circuit.

Controls

Addresses, data I/O’s, chip enables (E

, E

), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are

synchronous and are controlled by a positive edge triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Rev: 1.03 2/2000

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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