M7A3P1000-2PQ208 datasheet, PDF

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M7A3P1000-2PQ208: DescriptionField Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208; CategoryProgrammable logic devices Programmable logic; File Size306KB，8 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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M7A3P1000-2PQ208 Overview

Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208

M7A3P1000-2PQ208 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1822050847
package instruction	28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208
Reach Compliance Code	unknown
maximum clock frequency	350 MHz
JESD-30 code	S-PQFP-G208
JESD-609 code	e0
length	28 mm
Humidity sensitivity level	3
Configurable number of logic blocks	24576
Equivalent number of gates	1000000
Number of terminals	208
Maximum operating temperature	70 °C
Minimum operating temperature
organize	24576 CLBS, 1000000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	28 mm

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CoreAhbSram

Product Summary

Intended Use

•

Provides an Advanced Microcontroller Bus

Architecture (AMBA) Advanced High-Performance

Bus (AHB) Interface to the Embedded SRAM Blocks

within Fusion, IGLOO

, IGLOOe, IGLOO PLUS,

ProASIC

3, ProASIC3E, and ProASIC3L devices

Core Verification

•

A Bus Functional Model (BFM) Scriplet File Is

Included with the Core. This File Contains

Commands which Exercise and Test the Core

during BFM-Based Simulation of Processor

Systems, which Instantiate the Core along with

One of Actel's ARM

-Based Processor Cores, such

as CoreMP7 or Cortex

-M1.

Key Features

•

Implements Standard Slave AHB Bus Hardware

Interface

32-Bit Interface, Allowing Byte, Halfword, or Word

Accesses to SRAM

Ability to Logically Merge Multiple SRAM Blocks

into One Large Area of SRAM

Memory Size Can Be Configured from 2048 bytes

to 32768 bytes, in Steps of 2048 bytes

Contents

General Description ...................................................

Device Utilization and Performance ........................

I/O Signal Descriptions ...............................................

Generic/Parameter Descriptions ................................

Timing Diagrams ........................................................

Ordering Information ................................................

List of Changes ...........................................................

Datasheet Categories .................................................

Supported Device Families

•

Fusion

IGLOO, IGLOOe, IGLOO PLUS

ProASIC3, ProASIC3E, ProASIC3L

General Description

CoreAhbSram provides an AHB bus interface to the

embedded SRAM blocks within Fusion, IGLOO, IGLOOe,

IGLOO PLUS, ProASIC3, ProASIC3E, and ProASIC3L

devices. In these devices, software running on an AHB-

based microprocessor will be able to read and write the

embedded SRAM. Note that this datasheet focuses on

the operation of the CoreAhbSram and does not provide

detailed information on the structure or the behavior of

the Fusion, IGLOO, IGLOOe, IGLOO PLUS, ProASIC3L,

ProASIC3, or ProASIC3E SRAM. Refer to the

Fusion Family

of Mixed-Signal FPGAs,

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology, IGLOOe Low-Power Flash

FPGAs with Flash*Freeze Technology, IGLOO PLUS Low-

Power Flash FPGAs with Flash*Freeze Technology,

Actel ProASIC3 FPGA,

datasheets for details on the

internal SRAM.

Core Deliverables

•

VHDL and Verilog Delivered as Plaintext or

Obfuscated RTL via Actel Libero

Integrated

Design Environment (IDE) Catalog Manager or

CoreConsole IP Deployment Platform

November 2008

v 2 .2

M7A3P1000-2PQ208 Related Products

	M7A3P1000-2PQ208	M7A3P1000-1FG256	M7A3P1000-2PQ208I	M7A3P1000-2FG256I	M7A3P1000-2FG144I	M7A3P1000-2FG484	M7A3P1000-2FGG256	M7A3P1000-2FGG144	M7A3P1000-1FG144
Description	Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208		FPGA - Field Programmable Gate Array ProASIC3	FPGA - Field Programmable Gate Array ProASIC3	FPGA - Field Programmable Gate Array ProASIC3	FPGA - Field Programmable Gate Array ProASIC3	FPGA - Field Programmable Gate Array ProASIC3	FPGA - Field Programmable Gate Array ProASIC3	FPGA - Field Programmable Gate Array ProASIC3
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	conform to	conform to	incompatible
package instruction	28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208	BGA,	28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-208	BGA,	LBGA,	BGA,	BGA,	LBGA,	LBGA,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	compliant	compliant	compliant	unknown
maximum clock frequency	350 MHz	350 MHz	350 MHz	350 MHz	350 MHz	350 MHz	350 MHz	350 MHz	350 MHz
JESD-30 code	S-PQFP-G208	S-PBGA-B256	S-PQFP-G208	S-PBGA-B256	S-PBGA-B144	S-PBGA-B484	S-PBGA-B256	S-PBGA-B144	S-PBGA-B144
length	28 mm	17 mm	28 mm	17 mm	13 mm	23 mm	17 mm	13 mm	13 mm
Configurable number of logic blocks	24576	24576	24576	24576	24576	24576	24576	24576	24576
Equivalent number of gates	1000000	1000000	1000000	1000000	1000000	1000000	1000000	1000000	1000000
Number of terminals	208	256	208	256	144	484	256	144	144
Maximum operating temperature	70 °C	70 °C	85 °C	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C
organize	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES	24576 CLBS, 1000000 GATES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	BGA	FQFP	BGA	LBGA	BGA	BGA	LBGA	LBGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, FINE PITCH	GRID ARRAY	FLATPACK, FINE PITCH	GRID ARRAY	GRID ARRAY, LOW PROFILE	GRID ARRAY	GRID ARRAY	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.1 mm	1.8 mm	4.1 mm	1.7 mm	1.55 mm	2.44 mm	1.8 mm	1.55 mm	1.55 mm
Maximum supply voltage	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
Minimum supply voltage	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	BALL	GULL WING	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.5 mm	1 mm	0.5 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	QUAD	BOTTOM	QUAD	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	28 mm	17 mm	28 mm	17 mm	13 mm	23 mm	17 mm	13 mm	13 mm
JESD-609 code	e0	-	-	-	e0	e0	e1	e1	e0
Humidity sensitivity level	3	3	-	3	3	3	3	3	3
Terminal surface	TIN LEAD	TIN LEAD/TIN LEAD SILVER	-	TIN LEAD/TIN LEAD SILVER	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Lead (Sn/Pb)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead/Silver (Sn/Pb/Ag)
Maker	-	Microsemi	Microsemi	Microsemi	Microsemi	-	-	-	Microsemi
Peak Reflow Temperature (Celsius)	-	225	-	225	225	225	260	260	225
Maximum time at peak reflow temperature	-	30	-	30	30	30	40	40	30

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