CoreAhbSram
Product Summary
Intended Use
•
Provides an Advanced Microcontroller Bus
Architecture (AMBA) Advanced High-Performance
Bus (AHB) Interface to the Embedded SRAM Blocks
within Fusion, IGLOO
®
, IGLOOe, IGLOO PLUS,
ProASIC
®
3, ProASIC3E, and ProASIC3L devices
Core Verification
•
A Bus Functional Model (BFM) Scriplet File Is
Included with the Core. This File Contains
Commands which Exercise and Test the Core
during BFM-Based Simulation of Processor
Systems, which Instantiate the Core along with
One of Actel's ARM
®
-Based Processor Cores, such
as CoreMP7 or Cortex
TM
-M1.
Key Features
•
•
•
•
Implements Standard Slave AHB Bus Hardware
Interface
32-Bit Interface, Allowing Byte, Halfword, or Word
Accesses to SRAM
Ability to Logically Merge Multiple SRAM Blocks
into One Large Area of SRAM
Memory Size Can Be Configured from 2048 bytes
to 32768 bytes, in Steps of 2048 bytes
Contents
General Description ...................................................
Device Utilization and Performance ........................
I/O Signal Descriptions ...............................................
Generic/Parameter Descriptions ................................
Timing Diagrams ........................................................
Ordering Information ................................................
List of Changes ...........................................................
Datasheet Categories .................................................
1
1
2
2
3
3
3
4
Supported Device Families
•
•
•
Fusion
IGLOO, IGLOOe, IGLOO PLUS
ProASIC3, ProASIC3E, ProASIC3L
General Description
CoreAhbSram provides an AHB bus interface to the
embedded SRAM blocks within Fusion, IGLOO, IGLOOe,
IGLOO PLUS, ProASIC3, ProASIC3E, and ProASIC3L
devices. In these devices, software running on an AHB-
based microprocessor will be able to read and write the
embedded SRAM. Note that this datasheet focuses on
the operation of the CoreAhbSram and does not provide
detailed information on the structure or the behavior of
the Fusion, IGLOO, IGLOOe, IGLOO PLUS, ProASIC3L,
ProASIC3, or ProASIC3E SRAM. Refer to the
Fusion Family
of Mixed-Signal FPGAs,
IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology, IGLOOe Low-Power Flash
FPGAs with Flash*Freeze Technology, IGLOO PLUS Low-
Power Flash FPGAs with Flash*Freeze Technology,
or
Actel ProASIC3 FPGA,
datasheets for details on the
internal SRAM.
Core Deliverables
•
VHDL and Verilog Delivered as Plaintext or
Obfuscated RTL via Actel Libero
®
Integrated
Design Environment (IDE) Catalog Manager or
CoreConsole IP Deployment Platform
November 2008
© 2008 Actel Corporation
v 2 .2
1
CoreAhbSram
Device Utilization and Performance
Table 1 •
CoreAhbSram Device Utilization and Performance
SRAM Size
2 Kbytes (2048 bytes)
4 Kbytes (4096 bytes)
6 Kbytes (6144 bytes)
8 Kbytes (8192 bytes)
10 Kbytes (10240 bytes)
12 Kbytes (12288 bytes)
14 Kbytes (14336 bytes)
16 Kbytes (16384 bytes)
18 Kbytes (18432 bytes)
20 Kbytes (20480 bytes)
22 Kbytes (22528 bytes)
24 Kbytes (24576 bytes)
26 Kbytes (26624 bytes)
28 Kbytes (28672 bytes)
30 Kbytes (30720 bytes)
32 Kbytes (32768 bytes)
Tiles
201
207
251
207
256
265
320
234
283
283
330
294
359
349
443
297
Performance (MHz)
138
148
120
117
105
95
87
78
75
70
67
67
68
71
70
61
Note:
Tile counts and operating frequencies were obtained for an A3PE3000 device with a speed grade of -2.
I/O Signal Descriptions
The port signals for the CoreAhbSram core are described in
Table 2.
Table 2 •
CoreAhbSram Port Signals
Signal
HCLK
HRESETn
HADDR[14:0]
HTRANS[1:0]
Direction Description
Input
Input
Input
Input
Bus clock. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.
Reset. The bus reset signal is active low and is used to reset the system and the bus. This is the only
active low AHB signal.
This is a 15-bit bus which connects to the lower 15 bits of the 32-bit AHB system address bus.
Transfer type. Indicates the type of the current transfer:
00 – Idle
01 – Busy
10 – Non-Sequential
11 – Sequential
HWRITE
HSIZE[2:0]
HWDATA[31:0]
Input
Input
Input
Transfer direction. When high, this signal indicates a write transfer; and when low, a read transfer.
Transfer size. This indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or word
(32-bit).
32-bit data from the master
2
v2.2
CoreAhbSram
Table 2 •
CoreAhbSram Port Signals (Continued)
Signal
HREADYIN
HSEL
HRDATA[31:0]
HREADY
HRESP[1:0]
Direction Description
Input
Input
Output
Output
Output
Ready signal from all other AHB slaves
Combinatorial decode of HADDR, which indicates that this slave is currently selected
32-bit data written back to the master
Transfer done. When high, the HREADY signal indicates that a transfer has finished on the bus.
This signal can be driven low to extend a transfer.
Transfer response, which has the following meanings:
00 – Okay
01 – Error
10 – Retry
11 – Split
Generic/Parameter Descriptions
CoreAhbSram has two generics (VHDL) or two parameters (Verilog), called RAM_BLOCK_INSTANCES and FAMILY.
RAM_BLOCK_INSTANCES can take on the values shown in
Table 3.
FAMILY can take on the values shown in
Table 4 on
page 4.
If CoreAhbSram is instantiated within SmartDesign or CoreConsole, these generics/parameters are set by
selecting values within the configuration window. The device family is automatically set to the appropriate value
when working within SmartDesign or a CoreConsole project which has been initiated from within a Libero IDE project.
Table 3 •
RAM_BLOCK_INSTANCES Generic/Parameter Descriptions
RAM_BLOCK_INSTANCES
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
SRAM Size (Kbytes)
2 Kbytes (2048 bytes)
4 Kbytes (4096 bytes)
6 Kbytes (6144 bytes)
8 Kbytes (8192 bytes)
10 Kbytes (10240 bytes)
12 Kbytes (12288 bytes)
14 Kbytes (14336 bytes)
16 Kbytes (16384 bytes)
18 Kbytes (18432 bytes)
20 Kbytes (20480 bytes)
22 Kbytes (22528 bytes)
24 Kbytes (24576 bytes)
26 Kbytes (26624 bytes)
28 Kbytes (28672 bytes)
30 Kbytes (30720 bytes)
32 Kbytes (32768 bytes)
Note:
SRAM Size (Kbytes): Each SRAM block is 4 kbits in size, which is equal to 0.5 Kbytes.
v2.2
3
CoreAhbSram
Table 4 •
FAMILY Generic/Parameter Descriptions
FAMILY
15
16
17
20
21
22
23
Device Family
ProASIC3
ProASIC3E
Fusion
IGLOO
IGLOOe
ProASIC3L
IGLOO PLUS
The number of embedded SRAM blocks available varies according to the size of the device being used. Please refer to
the device family datasheets, available at
www.actel.com,
for information on the amount of SRAM available on each
device.
CoreAhbSram is usually instantiated as part of a processor-based system. Actel’s ARM-based CoreMP7 and Cortex-M1
processor cores each consume 4 blocks of embedded SRAM, which is equivalent to 2048 bytes. The user must take this
into account when determining the maximum memory configuration size which can be used for the CoreAhbSram
instances in the design. If a design uses a greater number of embedded SRAM blocks than are available on the device
being targeted, an error message will be generated when attempting to compile the design with Actel’s Designer tool.
Timing Diagrams
The timing diagrams for CoreAhbSram are the normal AHB read and write timing diagrams available in the AHB
specification from ARM. For more information on AMBA specifications, refer to
www.arm.com.
Ordering Information
CoreAhbSram is included in the SysBASIC core bundle that is supplied with the Actel CoreConsole IP Deployment
Platform tool. The obfuscated RTL version of SysBASIC (SysBASIC-OC) is available for free with CoreConsole. The source
RTL version of SysBASIC (SysBASIC-RM) can be ordered through your local Actel sales representative.
4
v2.2
CoreAhbSram
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v 2 .2 )
v2.2
The
"Product Summary" section
was updated to include IGLOO PLUS.
The
"General Description" section
was updated to include IGLOO PLUS.
Table 1
was updated to include additional SRAM sizes.
The
"Generic/Parameter Descriptions" section
was updated to add the "FAMILY" generic/
parameter.
Table 4
was updated to remove references to Cortex-M1 and M7 and add the "FAMILY" generic/
parameter description.
v2.0
The
"Product Summary" section
was updated to include ProASIC3L.
The
"General Description" section
was updated to include ProASIC3L.
Advanced v0.1
The
"Product Summary" section
was updated to include Cortex-M1 and IGLOO/e information.
The
"General Description" section
was updated to include IGLOO/e information.
Table 4
was updated to add Cortex-M1 information in the M7 Core column.
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RF/Wirelessly
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