SN74AUP1G125DRLR datasheet, PDF

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SN74AUP1G125DRLR: DescriptionLow-Power Single Bus Buffer Gate with 3-State Output 5-SOT-5X3 -40 to 85; Categorylogic logic; File Size3MB，50 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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SN74AUP1G125DRLR Overview

Low-Power Single Bus Buffer Gate with 3-State Output 5-SOT-5X3 -40 to 85

SN74AUP1G125DRLR Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOT
package instruction	VSOF, FL6,.047,20
Contacts	5
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	1 week
Control type	ENABLE LOW
Counting direction	UNIDIRECTIONAL
series	AUP/ULP/V
JESD-30 code	R-PDSO-F5
JESD-609 code	e4
length	1.6 mm
Load capacitance (CL)	30 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.004 A
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of ports	2
Number of terminals	5
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	VSOF
Encapsulate equivalent code	FL6,.047,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
method of packing	TR
Peak Reflow Temperature (Celsius)	260
power supply	1.2/3.3 V
Prop。Delay @ Nom-Sup	21.4 ns
propagation delay (tpd)	21.4 ns
Certification status	Not Qualified
Maximum seat height	0.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	FLAT
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	1.2 mm
Base Number Matches	1

SN74AUP1G125DRLR Related Products

	SN74AUP1G125DRLR	SN74AUP1G125YZPR	SN74AUP1G125YZTR	SN74AUP1G125DBVR
Description	Low-Power Single Bus Buffer Gate with 3-State Output 5-SOT-5X3 -40 to 85	Low-Power Single Bus Buffer Gate with 3-State Output 5-DSBGA -40 to 85	Low-Power Single Bus Buffer Gate with 3-State Output 5-DSBGA -40 to 85	Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin SOT-23 T/R
Brand Name	Texas Instruments	Texas Instruments	Texas Instruments	-
Is it Rohs certified?	conform to	conform to	conform to	-
Parts packaging code	SOT	BGA	BGA	-
package instruction	VSOF, FL6,.047,20	DSBGA-5	DSBGA-5	-
Contacts	5	5	5	-
Reach Compliance Code	compliant	compliant	compliant	-
ECCN code	EAR99	EAR99	EAR99	-
Factory Lead Time	1 week	1 week	1 week	-
Control type	ENABLE LOW	ENABLE LOW	ENABLE LOW	-
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	-
JESD-30 code	R-PDSO-F5	R-XBGA-B5	R-XBGA-B5	-
JESD-609 code	e4	e1	e1	-
length	1.6 mm	1.4 mm	1.4 mm	-
Load capacitance (CL)	30 pF	30 pF	30 pF	-
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	-
MaximumI(ol)	0.004 A	0.004 A	0.0017 A	-
Humidity sensitivity level	1	1	1	-
Number of digits	1	1	1	-
Number of functions	1	1	1	-
Number of ports	2	2	2	-
Number of terminals	5	5	5	-
Maximum operating temperature	85 °C	85 °C	85 °C	-
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-
Output characteristics	3-STATE	3-STATE	3-STATE	-
Output polarity	TRUE	TRUE	TRUE	-
Package body material	PLASTIC/EPOXY	UNSPECIFIED	UNSPECIFIED	-
encapsulated code	VSOF	VFBGA	VFBGA	-
Encapsulate equivalent code	FL6,.047,20	BGA5,2X3,20	BGA5,2X3,20	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE, VERY THIN PROFILE	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	-
method of packing	TR	TR	TAPE AND REEL	-
Peak Reflow Temperature (Celsius)	260	260	260	-
power supply	1.2/3.3 V	1.2/3.3 V	1.2/3.3 V	-
Prop。Delay @ Nom-Sup	21.4 ns	21.4 ns	21.4 ns	-
propagation delay (tpd)	21.4 ns	21.4 ns	21.4 ns	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	0.6 mm	0.5 mm	0.625 mm	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	0.8 V	0.8 V	0.8 V	-
Nominal supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	-
surface mount	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	-
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	-
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	-
Terminal form	FLAT	BALL	BALL	-
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	-
Terminal location	DUAL	BOTTOM	BOTTOM	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
width	1.2 mm	0.9 mm	0.9 mm	-

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