KM68V4000C, KM68U4000C Family
512K×8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology : TFT
•
Organization : 512K×8
•
Power Supply Voltage
KM68V4000C Family : 3.0~3.6V
KM68U4000C Family : 2.7~3.3V
•
Low Data Retention Voltage : 2V(Min)
•
Three state output and TTL Compatible
•
Package Type : 32-SOP-525, 32-TSOP2-400F/R
32-TSOP1-0820F, 32-TSOP1-0813.4F
CMOS SRAM
GENERAL DESCRIPTION
The KM68V4000C and KM68U4000C families are fabricated
by SAMSUNG′s advanced CMOS process technology. The
families support various operating temperature range and have
various package type for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
KM68V4000CL-L
KM68V4000CLI-L
KM68U4000CL-L
KM68U4000CLI-L
Operating Temperature Vcc Range
Commercial(0~70°C)
Industrial(-40~85°C)
Commercial(0~70°C)
Industrial(-40~85°C)
3.0~3.6V
3.0~3.6V
2.7~3.3V
2.7~3.3V
Speed(ns)
70
1)
/85
70 /85
70 /85/100
70
1)
/85/100
1)
1)
Standby
(I
SB1
, Max)
15µA
20µA
15µA
20µA
Operating
(I
CC2
, Max)
PKG Type
30mA
32-SOP
32-TSOP2-F/R
32-TSOP1-F
32-sTSOP1-F
1. The paramerter is measured with 30pF test load.
PIN DESCRIPTION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A0
A1
A4
A5
A6
A7
A12
A14
A16
A18
32-SOP
32-TSOP2
(Forward)
32-TSOP2
(Reverse)
7
8
9
10
11
12
13
14
15
16
Row
select
Memory array
1024 rows
512×8 columns
I/O
1
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
I/O
8
Data
cont
I/O Circuit
Column select
32-TSOP1
32-
S
TSOP1
(Forward)
Data
cont
A2 A3 A8 A9 A10 A11 A13 A15 A17
CS
WE
Control
logic
Name
Function
Name
Vcc
Vss
Function
Power
Ground
OE
A
0
~A
18
Address Inputs
WE
CS
OE
Write Enable Input
Chip Select Input
Output Enable Input
I/O
1
~I/O
8
Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.0
January 1999
KM68V4000C, KM68U4000C Family
PRODUCT LIST
Commercial Temp Products(0~70°C)
Part Name
KM68V4000CLG-7L
KM68V4000CLG-8L
KM68V4000CLT-7L
KM68V4000CLT-8L
KM68V4000CLR-7L
KM68V4000CLR-8L
KM68V4000CLY-7L
KM68V4000CLY-8L
KM68V4000CLTG-7L
KM68V4000CLTG-8L
KM68U4000CLG-7L
KM68U4000CLG-8L
KM68U4000CLG-10L
KM68U4000CLT-7L
KM68U4000CLT-8L
KM68U4000CLT-10L
KM68U4000CLR-7L
KM68U4000CLR-8L
KM68U4000CLR-10L
KM68U4000CLY-7L
KM68U4000CLY-8L
KM68U4000CLY-10L
KM68U4000CLTG-7L
KM68U4000CLTG-8L
KM68U4000CLTG-10L
Function
32-SOP, 70ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL
32-SOP, 70ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
CMOS SRAM
Industrial Temp Products(-40~85°C)
Part Name
Function
32-SOP, 70ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL
32-SOP, 70ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL
KM68V4000CLGI-7L
KM68V4000CLGI-8L
KM68V4000CLTI-7L
KM68V4000CLTI-8L
KM68V4000CLRI-7L
KM68V4000CLRI-8L
KM68V4000CLYI-7L
KM68V4000CLYI-8L
KM68V4000CLTGI-7L
KM68V4000CLTGI-8L
KM68U4000CLGI-7L
KM68U4000CLGI-8L
KM68U4000CLGI-10L
KM68U4000CLTI-7L
KM68U4000CLTI-8L
KM68U4000CLTI-10L
KM68U4000CLRI-7L
KM68U4000CLRI-8L
KM68U4000CLRI-10L
KM68U4000CLYI-7L
KM68U4000CLYI-8L
KM68U4000CLYI-10L
KM68U4000CLTGI-7L
KM68U4000CLTGI-8L
KM68U4000CLTGI-10L
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
OE
X
1)
H
L
X
1)
WE
X
1)
H
H
L
I/O
High-Z
High-Z
Dout
Din
Mode
Deselected
Output Disabled
Read
Write
Power
Standby
Active
Active
Active
1. X means don′t care (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
Remark
-
-
-
-
KM68V4000CL, KM68U4000CL
KM68V4000CLI, KM68U4000CLI
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
January 1999
KM68V4000C, KM68U4000C Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
KM68V4000C Family
KM68U4000C Family
All Family
KM68V4000C, KM68U4000C Family
KM68V4000C, KM68U4000C Family
Min
3.0
2.7
0
2.2
-0.3
3)
Typ
3.3
3.0
0
-
-
CMOS SRAM
Max
3.6
3.3
0
Vcc+0.3
2)
0.6
Unit
V
V
V
V
Note:
1. Commercial Product : T
A
=0 to 70°C, otherwise specified
Industrial Product : T
A
=-40 to 85°C, otherwise specified
2. Overshoot : V
CC
+2.0V in case of pulse width
≤
30ns
3. Undershoot : -2.0V in case of pulse width
≤
30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current (CMOS)
1. Industrial product = 20µA
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
Test Conditions
Min
-1
-1
-
-
-
-
2.2
-
-
Typ
-
-
-
-
-
-
-
-
-
Max
1
1
4
4
30
0.4
-
0.3
15
1)
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
CS=V
IH
or OE=V
IH
or WE=V
IL
V
IO
=Vss to Vcc
I
IO
=0mA, CS=V
IL
, V
IN
=V
IL
or V
IH
, Read
Cycle time=1µs, 100% duty, I
IO
=0mA CS≤0.2V,V
IN
≤0.2V
or V
IN
≥Vcc-0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
I
OL
=2.1mA
I
OH
=-1.0mA
CS=V
IH
, Other inputs = V
IL
or V
IH
CS≥Vcc-0.2V, Other inputs=0~Vcc
4
Revision 1.0
January 1999
KM68V4000C, KM68U4000C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
C
L
1)
=30pF+1TTL
1. 70ns product
CMOS SRAM
C
L
1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
(KM68V4000C Family : Vcc=3.0~3.6V, KM68U4000C Family : Vcc=2.7~3.3V
Commercial product :T
A
=0 to 70°C, Industrial product : T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
70ns
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
60
0
60
55
0
0
30
0
5
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
Min
85
-
-
-
10
5
0
0
10
85
70
0
70
55
0
0
35
0
5
85ns
Max
-
85
85
40
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
100ns
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
Max
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
1. Industrial product = 20µA
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS≥Vcc-0.2V
Vcc=3.0V, CS≥Vcc-0.2V
See data retention waveform
Min
2.0
-
0
5
Typ
-
0.5
-
-
Max
3.6
15
1)
-
-
Unit
V
µA
ms
5
Revision 1.0
January 1999
MCU
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