HY57V653220BLTC-10 datasheet, PDF

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HY57V653220BLTC-10: DescriptionSynchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86; Categorystorage storage; File Size78KB，10 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V653220BLTC-10 Overview

Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86

HY57V653220BLTC-10 Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	86
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
JESD-30 code	R-PDSO-G86
JESD-609 code	e6
length	22.22 mm
memory density	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	86
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX32
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
width	10.16 mm
Base Number Matches	1

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HY57V653220B

4 Banks x 512K x 32Bit Synchronous DRAM

Preliminary

DESCRIPTION

The Hyundai HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applica-

tions which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.

HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

JEDEC standard 3.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 86pin TSOP-II with 0.5mm of

pin pitch

All inputs and outputs referenced to positive edge of

system clock

Data mask function by DQM0,1,2 and 3

Internal four banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

•

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

•

ORDERING INFORMATION

Part No.

HY57V653220BTC-6

HY57V653220BTC-7

HY57V653220BTC-8

HY57V653220BTC-10

HY57V653220BLTC-6

HY57V653220BLTC-7

HY57V653220BLTC-8

HY57V653220BLTC-10

Clock Frequency

166MHz

143MHz

Power

Organization

Interface

Package

Normal

125MHz

100MHz

166MHz

143MHz

Low power

125MHz

100MHz

4Banks x 512Kbits

x32

LVTTL

400mil 86pin TSOP II

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.7/Apr.99

HY57V653220BLTC-10 Related Products

	HY57V653220BLTC-10	HY57V653220BLTC-6	HY57V653220BLTC-7	HY57V653220BLTC-8
Description	Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86	Synchronous DRAM, 2MX32, 5.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86	Synchronous DRAM, 2MX32, 5.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86	Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86
Maker	SK Hynix	SK Hynix	SK Hynix	SK Hynix
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,	TSOP2,	TSOP2,
Contacts	86	86	86	86
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	5.5 ns	5.5 ns	6 ns
JESD-30 code	R-PDSO-G86	R-PDSO-G86	R-PDSO-G86	R-PDSO-G86
JESD-609 code	e6	e6	e6	e6
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	67108864 bit	67108864 bit	67108864 bit	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	32	32	32	32
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	86	86	86	86
word count	2097152 words	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000	2000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	2MX32	2MX32	2MX32	2MX32
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH	TIN BISMUTH
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Base Number Matches	1	1	1	1

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