HD74HC393FP datasheet, PDF - EEWORLD Datasheet

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HD74HC393FP: DescriptionHC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, FP-14DA; Categorylogic logic; File Size83KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HD74HC393FP Overview

HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, FP-14DA

HD74HC393FP Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	FP-14DA
Contacts	14
Reach Compliance Code	compliant
ECCN code	EAR99
Counting direction	UP
series	HC/UH
JESD-30 code	R-PDSO-G14
length	10.06 mm
Load capacitance (CL)	50 pF
Load/preset input	NO
Logic integrated circuit type	BINARY COUNTER
Maximum Frequency@Nom-Sup	20000000 Hz
MaximumI(ol)	0.004 A
Operating mode	ASYNCHRONOUS
Humidity sensitivity level	1
Number of digits	4
Number of functions	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP14,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	2/6 V
propagation delay (tpd)	325 ns
Certification status	Not Qualified
Maximum seat height	2.2 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	5.5 mm
Base Number Matches	1

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HD74HC393

Dual 4-bit Binary Counters

REJ03D0625-0200

(Previous ADE-205-504)

Rev.2.00

Mar 30, 2006

Description

The HD74HC393 contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256

counter.

The HD74HC393 is incremented on the high to low transition (negative edge) of the clock input, and each has an

independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count

truncation and allows the implementation of divide-by-N counter configurations.

Features

•

High Speed Operation: t

(A to Q

) = 16 ns typ (C

= 50 pF)

•

High Output Current: Fanout of 10 LSTTL Loads

•

Wide Operating Voltage: V

= 2 to 6 V

•

Low Input Current: 1

µA

max

•

Low Quiescent Supply Current: I

(static) = 4

µA

max (Ta = 25°C)

•

Ordering Information

Part Name

HD74HC393P

HD74HC393FPEL

Package Type

DILP-14 pin

SOP-14 pin (JEITA)

Package Code

(Previous Code)

PRDP0014AB-B

(DP-14AV)

PRSP0014DF-B

(FP-14DAV)

Package

Abbreviation

—

EL (2,000 pcs/reel)

Taping Abbreviation

(Quantity)

Note: Please consult the sales office for the above package availability.

Function Table

Clock

Clear

Note:

1. H; High level, L; Low level, X; Irrelevant

Outputs

No change

Advance to next state

Rev.2.00 Mar 30, 2006 page 1 of 6

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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