PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS F
ANOUT
B
UFFER
F
EATURES
•
18 LVCMOS outputs, 23Ω typical output impedance
•
Selectable LVCMOS_CLK or LVPECL clock inputs
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency up to 250MHz
•
Output skew: 150ps (maximum)
•
Part to part skew: 750ps (maximum)
•
Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Pin compatible with the MPC940L
G
ENERAL
D
ESCRIPTION
The ICS83940 is a low skew, 1-to-18 LVPECL-
to-LVCMOS Fanout Buffer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83940 has two se-
lectable clock inputs. The PCLK, nPCLK pair can
accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines.
,&6
The ICS83940 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes. Guaran-
teed output and part-to-part skew characteristics make the
ICS83940 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
GND
V
DDO
Q0
Q1
Q2
Q3
Q4
Q5
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
GND
18
Q0 - Q17
1
32 31 30 29 28 27 26 25
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q17
Q16
Q15
GND
Q14
Q13
Q12
V
DDO
24
23
22
Q6
Q7
Q8
V
DD
Q9
Q10
Q11
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
ICS83940
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940AY
www.icst.com/products/hiperclocks.html
1
REV. D DECEMBER 21, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS F
ANOUT
B
UFFER
Name
GND
Power
Input
Input
Input
Input
Power
Power
Output
Type
Description
Power supply ground. Connect to ground.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup
Inver ting differential LVPECL clock input.
Positive supply pins. Connect to 3.3V or 2.5V.
Output supply pins. Connect to 3.3V or 2.5V.
Clock outputs. 23
Ω
typical output impedance.
LVCMOS interface levels
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 12, 17, 25
3
4
5
6
7, 21
8, 16, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
NOTE:
Pullup
and
Pulldow
n refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
Typical
Maximum
4
V
DD
, V
DDO
= 3.465V
10
51
51
23
Units
pF
pF
KΩ
KΩ
Ω
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
PCLK, nPCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
0
0
0
0
0
1
LVCMOS_CLK
—
—
—
—
—
—
0
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
—
nPCLK
1
0
Biased;
NOTE 1
Biased;
NOTE 1
0
1
—
Outputs
Q0 thru Q17
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
Non Inver ting
1
1
—
—
HIGH
Single Ended to Single Ended Non Inver ting
NOTE 1: Please refer to the Application Information section on page 11, Figure 8, which discusses wiring the differential
input to accept single ended levels.
83940AY
www.icst.com/products/hiperclocks.html
2
REV. D DECEMBER 21, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, Tstg
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
DD
V
DDO
I
DD
I
DDO
Input Supply Voltage
Output Supply Voltage
Input Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
25
40
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
LVCMOS_CLK
CLK_SEL
LVCMOS_CLK
CLK_SEL
LVCMOS_CLK,
CLK_SEL
LVCMOS_CLK,
CLK_SEL
Test Conditions
Minimum
2
2
-0.3
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.135V, I
OH
= -20mA
V
DDO
= 3.135V, I
OH
= 20mA
-5
2.4
0.5
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.8
150
Units
V
V
V
V
µA
µA
V
V
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
I
IH
I
IL
V
PP
Input High Current
Input Low Current
PCLK
nPCLK
PCLK
nPCLK
Test Conditions
*V
DDx
= V
IN
= 3.465V
*V
DDx
= V
IN
= 3.465V
*V
DDx
= 3.465V, V
IN
= 0V
*V
DDx
= 3.465V, V
IN
= 0V
-5
-150
1
V
DD
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.3
Input Common Mode Voltage;
GND + 1.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE:
*V
DDx
denotes V
DD
and V
DDO
.
83940AY
www.icst.com/products/hiperclocks.html
3
REV. D DECEMBER 21, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS F
ANOUT
B
UFFER
Test Conditions
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
0
<
f
≤
200MHz
0
<
f
≤
200MHz
Measured on rising edge
@V
DDO
/2
Measured on rising edge
@V
DDO
/2
Minimum
Typical
Maximum
250
4.2
3.7
150
750
1.7
1.4
20% to 80%
20% to 80%
f
≤
134MHz
45
50
55
Units
MH z
ns
ns
ps
ps
ns
ns
ps
ps
%
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
f
MAX
Output Frequency
t
pLH
Propagation Delay;
2.5
2.3
t
sk(o)
t
sk(pp)
t
sk(pp)
t
R
t
F
odc
Output Skew; NOTE 3, 5
Par t-to-Par t Skew; NOTE 4, 5
Par t-to-Par t Skew;
NOTE 5, 6
Output Rise Time
Output Fall Time
Output Duty Cycle
PCLK, nPCLK
LVCMOS_CLK
134
<
f
≤
200MHz
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages,
same temperature, and with equal load conditions. Using the same type of inputs on each device, the
outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%; V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
DD
V
DDO
I
DD
I
DDO
Input Power Supply Voltage
Output Power Supply Voltage
Input Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
25
40
Units
V
V
mA
mA
T
ABLE
4E. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%; V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
83940AY
Test Conditions
LVCMOS_CLK
CLK_SEL
LVCMOS_CLK
CLK_SEL
LVCMOS_CLK,
CLK_SEL
LVCMOS_CLK,
CLK_SEL
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.8
150
Units
V
V
V
V
µA
µA
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 2.375V, I
OH
= -12mA
V
DDO
= 2.375V, I
OL
= 12mA
-5
1.8
0.5
V
www.icst.com/products/hiperclocks.html
4
REV. D DECEMBER 21, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS F
ANOUT
B
UFFER
Test Conditions
PCLK
nPCLK
PCLK
nPCLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
1
V
DD
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
T
ABLE
4F. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%; V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
I
IH
I
IL
V
PP
Input High Current
Input Low Current
Peak-to-Peak Input Voltage
0.3
Input Common Mode Voltage;
GND + 1.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%; V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol
f
MAX
tp
LH
Parameter
Output Frequency
Propagation Delay;
PCLK, nPCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
Test Conditions
0
<
f
≤
200MHz
0
<
f
≤
200MHz
Measured on rising edge
@V
DDO
/2
Measured on rising edge
@V
DDO
/2
150
750
1.8
1.8
20% to 80%
20% to 80%
f
≤
134MHz
45
55
Minimum Typical
Maximum
250
3.8
Units
MHz
ns
ns
ps
ps
ns
ns
ps
ps
%
2.0
t
sk(o)
t
sk(pp)
t
sk(pp)
t
R
t
F
odc
Output Skew; NOTE 3, 5
Par t-to-Par t Skew; NOTE 4, 5
Par t-to-Par t Skew;
NOTE 5, 6
Output Rise Time
Output Fall Time
Output Duty Cycle
PCLK, nPCLK
LVCMOS_CLK
134
<
f
≤
200MHz
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defined as skew between outputs at the same supply voltage, same temperature, and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
T
ABLE
4G. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
DD
V
DDO
I
DD
I
DDO
83940AY
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
25
40
Units
V
V
mA
mA
Input Supply Voltage
Output Supply Voltage
Input Supply Current
Output Supply Current
www.icst.com/products/hiperclocks.html
5
REV. D DECEMBER 21, 2001
京公网安备 11010802033920号
EEWORLD
