4M x 16-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
HYB 3164165T(L) -50/-60
HYB 3165165T(L) -50/-60
Preliminary Information
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4 194 304 words by 16-bit organization
0 to 70 ˚C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
Hyper page mode (EDO) cycle time
20 ns (-50 version)
25 ns (-60 version)
Single + 3.3 V (± 0.3V) power supply
Low power dissipation
max. 396 active mW ( HYB 3164165T(L)-50)
max. 360 active mW ( HYB 3164165T(L)-60)
max. 504 active mW ( HYB 3165165T(L)-50)
max. 432 active mW ( HYB 3165165T(L)-60)
7.2 mW standby (TTL)
720 W standby (MOS)
14.4 mW Self Refresh (L-version only)
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
Hyper page mode (EDO) capability
2 CAS / 1 WE byte control
8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165T(L))
4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165T(L))
Plastic Package:
P-TSOPII-54-1 500 mil
HYB 3164(5)165T(L)
Semiconductor Group
31
HYB3164(5)165T(L)-50/-60
4M x 16 EDO-DRAM
This HYB3164(5)165 is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is
fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process
technology. The circuit and process design allow this device to achieve high performance and low
power dissipation. The HYB3164(5)165 operates with a single 3.3 +/-0.3V power supply and
interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the
HYB3164(5)165 to be packaged in a 500mil wide TSOPII-54 plastic package. These packages
provide high system bit densities and are compatible with commonly used automatic testing and
insertion equipment.The HYB3164(5)165TL parts have a very low power „sleep mode“ supported
by Self Refresh.
Ordering Information
Type
HYB 3164165T-50
HYB 3164165T-60
HYB 3164165TL-50
HYB 3164165TL-60
HYB 3165165T-50
HYB 3165165T-60
HYB 3165165TL-50
HYB 3165165TL-60
Ordering
Code
on request
on request
on request
on request
on request
on request
on request
on request
Package
P-TSOPII-54-1
P-TSOPII-54-1
P-TSOPII-54-1
P-TSOPII-54-1
P-TSOPII-54-1
P-TSOPII-54-1
P-TSOPII-54-1
P-TSOPII-54-1
500 mil
500 mil
500 mil
500 mil
500 mil
500 mil
500 mil
500 mil
Descriptions
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
EDO-DRAM (access time 50 ns)
EDO-DRAM (access time 60 ns)
Pin Names
A0-A12
A0-A11
RAS
OE
I/O1-I/O16
UCAS, LCAS
WRITE
Vcc
Vss
Address Inputs for HYB 3164165T(L)
Address Inputs for HYB 3165165T(L)
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply ( + 3.3V)
Ground
Semiconductor Group
32
HYB3164(5)165T(L)-50/-60
4M x 16 EDO-DRAM
P-TSOPII-54-1 (500 mil)
* Pin 35 is A12 for HYB 3164165T(L) and N.C. for HYB 3165165T(L)
Pin Configuration
Semiconductor Group
33
HYB3164(5)165T(L)-50/-60
4M x 16 EDO-DRAM
TRUTH TABLE
FUNCTION
Standby
Read:Word
Read:Lower Byte
Read:Upper Byte
Write:Word
(Early-Write)
Write:Lower Byte
(Early-Write)
Write:Upper Byte
(Early Write)
Read-Modify-
Write
Hyper Page Mode
1st
Read (Word)
Cycle
Hyper Page Mode 2nd
Read (Word)
Cycle
Hyper Page Mode
1st
Early Write(Word) Cycle
Hyper Page Mode 2nd
Early Write(Word) Cycle
Hyper Page Mode
1st
RMW
Cycle
Hyper Page Mode
2st
RMW
Cycle
RAS only refresh
CAS-before-RAS
refresh
Test Mode Entry
Hidden Refresh
(Read)
Hidden Refresh
(Write)
Self Refresh
(L-version only)
RAS LCAS UCA
S
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H-X
L
L
H
L
L
H
L
H-L
H-L
H-L
H-L
H-L
H-L
H
H-X
H
H
L
L
H
L
L
H-L
H-L
H-L
H-L
H-L
H-L
H
L
L
L
L
H
WRIT
E
X
H
H
H
L
L
L
H-L
H
H
L
L
H-L
H-L
X
H
L
H
L
X
OE
X
L
L
L
X
X
X
ROW
ADD
X
ROW
ROW
ROW
ROW
ROW
ROW
COL
ADD
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
n/a
n/a
COL
COL
X
I/O1-
I/O16
High Impedance
Data Out
Lower Byte:Data Out
Upper-Byte:High-Z
Lower Byte:High-Z
Upper Byte:Data Out
Data In
Lower Byte:Data Out
Upper-Byte:High-Z
Lower Byte:High-Z
Upper Byte:Data Out
Data Out, Data In
Data Out
Data Out
Data In
Data In
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
High Impedance
Data Out
Data In
High Impedance
L - H ROW
L
L
X
X
ROW
n/a
ROW
n/a
L - H ROW
L - H n/a
X
X
X
L
X
X
ROW
X
X
ROW
ROW
X
H-L L
H-L L
L-H- L
L
L-H- L
L
H-L
L
Semiconductor Group
34
HYB3164(5)165T(L)-50/-60
4M x 16 EDO-DRAM
Block Diagram for HYB 3164165T(L)
Semiconductor Group
35
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