PRELIMINARY
MX98745
100 BASE-TX/FX
REPEATER CONTROLLER
1.0 FEATURES
• IEEE 802.3u D5 repeater and management compatible
• Support 7 TX/FX ports and 1 universal port (TX or MII
port selectable)
• Support 8-scale utilization and collision rate LED display
• Asynchronous Expansion port clock supported for
easily stackable application
• Separate jabber and partition state machines for each
port
• On-chip elasticity buffer for PHY signal re-timing to the
MX98745 clock source
• Contents of internal register loaded from EEPROM
• PCS/MAC type MII interface selectable
• CMOS device features high integration and low power
with a signle +5V supply
2.0 GENERAL DESCRIPTION
The MX98745, Second generation 100 Mb/s TX/FX Hub
Controller (XRC II), is designed specifically to meet the
needs of today's high speed Fast Ethernet networking
systems. The MX98745 is fully IEEE 802.3u D5 clause
27 repeater compatible.
Difference from MX98741, which provides 8 dedicated
TX/FX ports and 3 MII ports, MX98745 support 7 dedi-
cated TX/FX ports and one programmble TX/FX/MII port.
Whenever MII port is programmed, MX98745 also sup-
ports the flexibility to make user can easily select PCS or
MAC type MII for system application. With this program-
mable MII interface, user can easily connect MX98745 to
MX98742 (Bridge), or T4 transceiver. Or user can use
this programmable MII interface to connect to either MAC
or PCS type data transceiver.
All contents of internal registers are loaded from
EEPROM in MX98745. If system application prefers
default setting instead of using contents from EEPROM,
EEPROM operation can be disabled by setting EECONF
to low. This feature faciliates system modulization appli-
cation.
8 scale of utilization LED is also provided by MX98745.
They are 1%, 3%, 5%, 10%, 20%, 40%, 60% and 80+%.
The defination for utiliztion is Mbs Received/100 Mb within
one second sampling period. Meanwhile, RX/LINK, Par-
tition, Isolation and Collision status are also provided
through LED display.
A great improvement in MX98745 (compared to
MX98741) is that it also provides "synchronous expan-
sion port data transfer mode" to make stackable design
more easier.
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REV. 1.4, JUL. 8, 1998
1
MX98745
3.0 BLOCK DIAGRAMS
MDC
MDIO
LSCLK
SIGDET[7:0]
Jabber Clock Generator
RESEL
Port 0 5B RX/
Port 0 4B RX
SCRCTRL
Repeater Core
&
Control/Status
Registers
Port 0 5B RX/
Port 0 4B RX
TDAT0[4:0]
TXCLK
(MII Only)
RDAT0[4:0]
RSCLK0
Port 7 RX
Relative FUN
Port 7
Relative FUN
RDAT7[4:0]
RSCLK7
TDAT7[4:0]
Expansion Port Function
Utilization/ Status LED
Display FUN
EDACT JAMI EDAT[4:0] EPCLK JAMO EDENL EDCRS ANYACT LED[8:0]
LDSEL[2:0]
Figure 3-1 Block Diagram forMX98745
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2
MX98745
4.0 PIN CONFIGURATION
GND
RDAT30
RDAT31
RDAT32
RDAT33
RDAT34
GND
TDAT30
TDAT31
TDAT32
TDAT33
TDAT34
GND
RSCLK4
SIGDET4
VDD
RDAT40
RDAT41
RDAT42
RDAT43
RDAT44
TDAT40
TDAT41
TDAT42
TDAT43
TDAT44
GND
RSCLK5
SIGDET5
RDAT50
RDAT51
RDAT52
RDAT53
RDAT54
TDAT50
TDAT51
TDAT52
TDAT53
TDAT54
GND
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VDD
SIGDET3
RSCLK3
TDAT24
TDAT23
TDAT22
TDAT21
TDAT20
VDD
RDAT24
RDAT23
RDAT22
RDAT21
RDAT20
GND
SIGDET2
RSCLK2
VDD
TDAT14
TDAT13
TDAT12
TDAT11
TDAT10
GND
RDAT14
RDAT13
RDAT12
RDAT11
RDAT10
SIGDET1
RSCLK1
MON
LED7/PHY4
LED6/PHY3
LED5/PHY2
LED4/PHY1
LED3/PHY0
LED2/TXMII
LED1/PMSEL
GND
GND
RSCLK6
SIGDET6
RDAT60
RDAT61
RDAT62
RDAT63
RDAT64
TDAT60
TDAT61
TDAT62
TDAT63
TDAT64
GND
RSCLK7
SIGDET7
GND
RDAT70
RDAT71
RDAT72
RDAT73
RDAT74
VDD
TDAT70
TDAT71
TDAT72
TDAT73
TDAT74
VDD
LSCLK
IBMON
TSEL
TEST
XCOLED
SCRCTRL
RESETL
COL
MDO
MDIO
VDD
MX98745
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
LED0/EECLK/PARSEL
LDS2/ED0
GND
LDS1/EDI
LSD0/EECONF
LEDEN
VDD
EECS
EDACT
ANYACT
GND
EDENL
EDCRS
JAM1
JAM0
EPCLK
EDAT4
EDAT3
EDAT2
EDAT1
EDAT0
GND
TXEN
CRS
GND
TXCLK
TDAT04/TXER
TDAT03/TXD3
TDAT02/TXD2
TDAT01/TXD1
TDAT00/TXD0
EDAT04/RXER
RDAT03/RXD3
RDAT02/RXD2
RDAT01/RXD1
RDAT00/RXD0
SIGDET0/RXDV
RSCLK0
VDD
Figure 4-1 Pin Configuration for XRCII
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3
MX98745
5.0 PIN DESCRIPTION
A. MX Data Transceiver (Am78965/Am78966 or MC68836), 98 pins
PAD #
24-28
9-13
155-159
142-146
128-132
113-117
98-102
30
LSCLK
I,
TTL
I,
TTL
Local Synchrnous Clock. This pin supplies the frequency reference to
the MX98745 within same HUB. It should be driven by a crystal-
controlled 25M clock source.
Receive Data. These 5 bit parallel data symbol from transceiver are
latched by the rising edge of RSCLK of each port.
RDAT4 is the Most Significant Bit.
Name
TDAT[7:1][0:4]
I/O
O,
TTL
Description
Transmit Data. These five outputs are 5B encoded transmit data sym
bols, driven at the rising edge of LSCLK.
TDAT4 is the Most Significant Bit.
18-22
4-8
150-154
137-141
122-126
107-111
92-96
15,2
148,134
118,104
90,42
16,3,
149,135,
119,105,
91
31
RDAT[7:1][0:4]
RSCLK[7:0]
I,
TTL
Recovered Symbol Clock. This is a 25 MHz clock, which is derived
from the clock synchronization PLL circuit.
SIGDET[7:1]
I,
TTL
Signal Detect. This signal indicates that the received signal is above
the detection threshold and will be used for the link test state machine.
Monitor
I,
TTL
Monitor Mode. Internal Pulldown. When this pin is set to one, LED
display pins LED[9:0] will be changed to monitor mode.
Table 5-1 Pin Description for XRCII
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4
MX98745
B. Expansion Port, 12 pins
PAD #
65
Name
JAMO
I/O
O,
CMOS
I,
TTL
I,
Sche
I/O,
TTL
I/O,
TTL
O,
CMOS
I,
Sche
O,
CMOS
Description
Forced Jam Out. Active High. The OR’d forced jam signals controlled by
Carrier Integrity Monitor of each port. If collision occurs inside the XRC II
(exclude JAMI), this pin is also asserted.
Forced Jam Input. Active High. Asserted by external arbitor, and XRCII will
generate JAM patterns to all its ports whenever this signal is validate more
than 40 ns. This signal is filtered by LSCLK for 40ns internally.
Enable Expansion Data. Active Low. Asserted by an external arbitor. XRC II
will not drive data onto EDAT until this pin is asserted. Assertion time less
than 40ns will not be recognized by XRC II.
Expansion Data. Bidirectional 5 bit-wide data. By default, EDAT is an input.
An external arbitor coordinates multiple devices on EDAT.
Expansion port Data Clock. This clock will be outputed by XRCII along with
the EDAT[4:0]. Another module of XRCII should use this signal as expansion
port data input clock.
Any Activity. Active High. When XRCII tries to release data onto EDAT, this
pin will be asserted by XRC II.
Expansion Data Carrier Sense. When this pin is asserted, XRC II will
recognize that there is activity on expansion port data bus EDAT and perform
corresponding activity within XRCII itself.
Expansion Data Activity. When XRCII detects that EDENL is asserted by
external arbitor, it will assert EDACT high. System application can use this
signal to control the data bus flow of EDAT.
66
JAMI
68
EDENL
63-59
64
EDAT[4:0]
EPCLK
70
67
ANYACT
EDCRS
71
EDACT
Table 5-1 Pin Description for XRC II (Continued)
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REV. 1.4, JUL. 8, 1998
5
RF/Wirelessly
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