CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
VCC Supply Current
No Load Switching Supply Current
Standby Supply Current
IVCC
IVCC
f_PWM = 300kHz, V_VCC = 5V
PWM 0V to 2.5V transition, EN = High
PWM 0V to 2.5V transition, EN = Low
1.27
1.85
1.15
mA
mA
mA
POWER-ON RESET AND ENABLE
VCC Rising POR Threshold
VCC Falling POR Threshold
VCC POR Hysteresis
EN High Threshold
EN Low Threshold
PWM INPUT (See TIMING DIAGRAM" on page 6)
Input Current
IPWM
VPWM = 5V
VPWM = 0V
PWM Rising Threshold (Note 4)
PWM Falling Threshold (Note 4)
Three-State Lower Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Upper Gate Rising Threshold
Three-state Upper Gate Falling Threshold
UGATE Rise Time (Note 4)
t_RU
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V, 3nF load, 10% to 90%
500
-430
3.4
1.6
1.6
1.1
3.2
2.8
8
µA
µA
V
V
V
V
V
V
ns
3.2
3.0
130
1.40
1.20
3.8
3.4
300
1.65
1.35
4.4
4.0
530
1.90
1.55
V
V
mV
V
V
FN6494 Rev 0.00
April 25, 2008
Page 4 of 10
ISL6620, ISL6620A
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested.
(Continued)
SYMBOL
t_RL
t_FU
t_FL
t_PDHU
t_PDHL
t_PDLU
t_PDLL
t_LG_ON_DM
TEST CONDITIONS
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, adaptive
VCC = 5V, 3nF load, adaptive
VCC = 5V, 3nF load
VCC = 5V, 3nF load
VCC = 5V
230
MIN
TYP
8
8
4
40
23
18
25
330
450
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
Minimum Lgate on time at Diode emulation
OUTPUT (Note 4)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
NOTE:
I_U_Source
VCC = 5V, 3nF load
2
1
2
1
2
1
4
0.4
A
A
A
A
R_U_SOURCE 20mA source current
I_U_SINK
R_U_SINK
I_L_SOURCE
VCC = 5V, 3nF load
20mA sink current
VCC = 5V, 3nF load
R_L_SOURCE 20mA source current
I_L_SINK
R_L_SINK
VCC = 5V, 3nF load
20mA sink current
4. Limits should be considered typical and are not production tested.
Functional Pin Description
PACKAGE PIN #
SOIC
1
2
DFN
1
2
PIN
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
No connect.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation.
See “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output
of the controller.
Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to 5V bias supply. This pin supplies power to the upper gate and lower gate drive. Place a high
quality low ESR ceramic capacitor from this pin to GND.
Enable input pin. Connect this pin high to enable driver and low to disable driver.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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