74LVC3G07
Triple buffer with open-drain output
Rev. 03 — 01 February 2005
Product data sheet
1. General description
The 74LVC3G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC3G07 provides three non-inverting buffers.
The output of the device is an open drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
2. Features
s
s
s
s
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
−24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
s
s
s
s
s
s
s
s
Philips Semiconductors
74LVC3G07
Triple buffer with open-drain output
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol
t
PLZ
, t
PZL
Parameter
Conditions
Min
-
-
-
-
-
-
[1] [2]
Typ
2.9
1.7
2.3
2.1
1.5
2.5
6.5
Max
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
pF
pF
propagation delay
V
CC
= 1.8 V;
input nA to output nY C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V;
C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V;
C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V;
C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V;
C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
[1]
input capacitance
power dissipation
V
CC
= 3.3 V
capacitance per gate
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
[2]
The condition is V
I
= GND to V
CC
.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range
74LVC3G07DP
74LVC3G07DC
74LVC3G07GT
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
TSSOP8
VSSOP8
XSON8
Description
plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
×
1.95
×
0.5 mm
Version
SOT505-2
SOT765-1
SOT833-1
Type number
5. Marking
Table 3:
Marking codes
Marking code
V07
V07
V07
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Type number
74LVC3G07DP
74LVC3G07DC
74LVC3G07GT
9397 750 14542
Product data sheet
Rev. 03 — 01 February 2005
2 of 14
Philips Semiconductors
74LVC3G07
Triple buffer with open-drain output
6. Functional diagram
1
1A
1Y
7
1A
1
1
7
1Y
3
2A
2Y
5
2A
3
1
5
2Y
6
3A
3Y
2
3A
6
1
2
3Y
mnb136
mnb137
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Y
A
GND
mna591
Fig 3. Logic diagram (one driver)
7. Pinning information
7.1 Pinning
07
1A
1A
3Y
2A
GND
1
2
3
4
001aab022
1
8
V
CC
8
7
V
CC
1Y
3A
2Y
3Y
2
7
1Y
07
6
5
2A
3
6
3A
GND
4
5
2Y
001aac022
Transparent top view
Fig 4. Pin configuration VSSOP8 and
TSSOP8
Fig 5. Pin configuration XSON8
9397 750 14542
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 01 February 2005
3 of 14
Philips Semiconductors
74LVC3G07
Triple buffer with open-drain output
7.2 Pin description
reserved
Table 4:
Symbol
1A
3Y
2A
GND
2Y
3A
1Y
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
data input
data output
data input
ground (0 V)
data output
data input
data output
supply voltage
8. Functional description
8.1 Function table
Table 5:
Input nA
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
Function table
[1]
Output nY
L
Z
9. Limiting values
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
, I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input diode current
output diode current
output sink current
V
CC
or GND current
storage temperature
power dissipation
Conditions
[1]
Min
−0.5
−0.5
−0.5
−0.5
-
-
-
-
−65
Max
+6.5
+6.5
+6.5
+6.5
−50
−50
50
±100
+150
300
Unit
V
V
V
V
mA
mA
mA
mA
°C
mW
active mode
Power-down mode
V
I
< 0 V
V
O
< 0 V
V
O
= 0 V to 6.5 V
[1]
[1] [2]
T
amb
=
−40 °C
to +125
°C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
9397 750 14542
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 01 February 2005
4 of 14
Philips Semiconductors
74LVC3G07
Triple buffer with open-drain output
10. Recommended operating conditions
Table 7:
V
CC
V
I
V
O
T
amb
t
r
, t
f
Recommended operating conditions
Conditions
Min
1.65
0
active mode
Power-down mode; V
CC
= 0 V
ambient temperature
input rise and fall
times
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
0
0
−40
0
0
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
°C
ns/V
ns/V
supply voltage
input voltage
output voltage
Symbol Parameter
11. Static characteristics
Table 8:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level input
voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
µA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
LI
I
OZ
I
off
I
CC
∆I
CC
C
I
9397 750 14542
Min
Typ
Max
-
-
-
-
0.7
0.8
0.3
×
V
CC
0.1
0.45
0.3
0.4
0.55
0.55
±5
±10
±10
10
500
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
pF
5 of 14
T
amb
=
−40 °C
to +85
°C
[1]
0.65
×
V
CC
-
1.7
2.0
0.7
×
V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Rev. 03 — 01 February 2005
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1
±0.1
±0.1
0.1
5
2.5
0.35
×
V
CC
V
input leakage current
3-state output
OFF-state current
power-off leakage
current
quiescent supply
current
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V
V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND;
V
CC
= 5.5 V
V
I
or V
O
= 5.5 V; V
CC
= 0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional quiescent
V
I
= V
CC
−
0.6 V; I
O
= 0 A;
supply current per pin V
CC
= 2.3 V to 5.5 V
input capacitance
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
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