DDR SDRAM 256Mb D-die (x8, x16)
256Mb D-die Revision History
Revison 0.0 (June. 2002)
1. First release
Revison 0.1 (Aug. 2002)
- Changed IDD3P value from 40mA to 55m
- Changed IDD3N value from 60mA to 75mA
Revision 1.0 (February, 2003)
- Modified AC Timing Parameters and Idd value.
Revision 1.1 (February, 2003)
- Modified tAC value +/-0.7ns => +/-0.65ns
DDR SDRAM
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
Key Features
• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
DDR SDRAM
• 66pin TSOP II package
Ordering Information
Part No.
K4H560838D-TCCC
K4H560838D-TCC4
K4H561638D-TCCC
K4H561638D-TCC4
16M x 16
32M x 8
Org.
Max Freq.
CC(DDR400@CL=3)
C4(DDR400@CL=3)
CC(DDR400@CL=3)
C4(DDR400@CL=3)
SSTL2
66pin TSOP II
Interface
SSTL2
Package
66pin TSOP II
Operating Frequencies
- CC(DDR400@CL=3)
Speed @CL3
CL-tRCD-tRP
*CL : CAS Latency
200MHz
3-3-3
- C4(DDR400@CL=3)
200MHz
3-4-4
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
Pin Description
DDR SDRAM
16Mb x 16
32Mb x 8
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
Bank Address
BA0~BA1
Auto Precharge
A10
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
256Mb Package Pinout
Organization
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
Column Address
A0-A9
A0-A8
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 Feb. 2003
DDR SDRAM 256Mb D-die (x8, x16)
Package Physical Demension
DDR SDRAM
Units : Millimeters
(0.80)
(0.50)
#66
#34
10.16±0.10
(1.50)
(10×)
(10×)
#1
(1.50)
#33
(0.80)
0.125
+0.075
-0.035
0.665±0.05
0.210±0.05
(0.50)
(R
0.
15
)
0.05 MIN
[
0.075 MAX ]
(10×)
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
(R
(0.71)
0.65TYP
0.65±0.08
0.30±0.08
0.10 MAX
0.2
5)
0×~8×
66pin TSOPII / Package dimension
Rev. 1.1 Feb. 2003
(R
0.
25
)
(4
×
)
(R
0.1
5)
(10×)
1.20MAX
22.22±0.10
1.00±0.10
0.25TYP
0.45~0.75
11.76±0.20
(10.76)
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
