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PDM41024

Description
128K X 8 STANDARD SRAM, 15 ns, PDSO32
Categorystorage   
File Size115KB,8 Pages
ManufacturerETC
Download Datasheet Parametric View All

PDM41024 Overview

128K X 8 STANDARD SRAM, 15 ns, PDSO32

PDM41024 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals32
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
maximum access time15 ns
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE
surface mountYes
Terminal formJ BEND
terminal coatingNOT SPECIFIED
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
memory width8
organize128K X 8
storage density1.05E6 deg
operating modeASYNCHRONOUS
Number of digits131072 words
Number of digits128K
Memory IC typeSTANDARD SRAM
serial parallelPARALLEL
PDM41024
1 Megabit Static RAM
128K x 8-Bit
Features
n
1
2
3
4
5
6
7
Description
The PDM41024 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE1) inputs are both LOW and CE2 is
HIGH. Reading is accomplished when WE and CE2
remain HIGH and CE1 and OE are both LOW.
The PDM41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41024 comes in two versions:
the standard power version (SA) and the low power
version (LA). The two versions are functionally the
same and differ only in their power consumption.
The PDM41024 is available in a 32-pin plastic TSOP
(I), and a 300-mil and 400-mil plastic SOJ.
High-speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
Low power operation (typical)
- PDM41024SA
Active: 450 mW
Standby: 50 mW
- PDM41024LA
Active: 400 mW
Standby: 25mW
Single +5V (
±
10%) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP (I)- T
n
n
n
n
Functional Block Diagram
A
0
A
16
Decoder
Addresses
Memory
Matrix
8
9
10
I/O
0
I/O
7
• • • • •
Input
Data
Control
Column I/O
11
12
1
CE1
CE2
WE
OE
Control
Rev. 3.3 - 4/09/98
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