MCP23017/MCP23S17
16-Bit I/O Expander with Serial Interface
Features
• 16-bit remote bidirectional I/O port
- I/O pins default to input
• High-speed I
2
C™ interface (MCP23017)
- 100 kHz
- 400 kHz
- 1.7 MHz
• High-speed SPI interface (MCP23S17)
- 10 MHz (max.)
• Three hardware address pins to allow up to eight
devices on the bus
• Configurable interrupt output pins
- Configurable as active-high, active-low or
open-drain
• INTA and INTB can be configured to operate
independently or together
• Configurable interrupt source
- Interrupt-on-change from configured register
defaults or pin changes
• Polarity Inversion register to configure the polarity
of the input port data
• External Reset input
• Low standby current: 1 µA (max.)
• Operating voltage:
- 1.8V to 5.5V @ -40°C to +85°C
- 2.7V to 5.5V @ -40°C to +85°C
- 4.5V to 5.5V @ -40°C to +125°C
Package Types
PDIP,
SOIC,
SSOP
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
V
DD
V
SS
NC
SCL
SDA
NC
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
A1
A0
MCP23017
QFN
GPB4
GPB5
GPB6
GPB7
V
DD
V
SS
NC
1
2
3
4
5
6
7
28 27 26 25 24 23 22
21
20
19
MCP23017
18
17
16
15
8 9 10 11 121314
SCL
SDA
NC
A0
A1
A2
RESET
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
PDIP,
SOIC,
SSOP
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
GPA5
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCP23017
Packages
•
•
•
•
28-pin PDIP (300 mil)
28-pin SOIC (300 mil)
28-pin SSOP
28-pin QFN
MCP23S17
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
V
DD
V
SS
CS
SCK
SI
SO
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
A1
A0
QFN
GPB4
GPB5
GPB6
GPB7
V
DD
V
SS
CS
1
2
3
4
5
6
7
28 27 26 25 24 23 22
21
20
19
MCP23S17
18
17
16
15
8 9 10 11 121314
SCK
SI
SO
A0
A1
A2
RESET
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
GPA5
MCP23S17
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
©
2007 Microchip Technology Inc.
DS21952B-page 1
MCP23017/MCP23S17
Functional Block Diagram
MCP23S17
CS
SCK
SI
SO
SPI
MCP23017
SCL
SDA
3
A2:A0
RESET
INTA
INTB
Interrupt
Logic
8
GPIO
Configuration/
Control
Registers
Decode
Control
16
I
2
C™
Serializer/
Deserializer
GPIO
GPB7
GPB6
GPB5
GPB4
GPB3
GPB2
GPB1
GPB0
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
DS21952B-page 2
©
2007 Microchip Technology Inc.
MCP23017/MCP23S17
1.0
DEVICE OVERVIEW
The MCP23017/MCP23S17 (MCP23X17) device
family provides 16-bit, general purpose parallel I/O
expansion for I
2
C bus or SPI applications. The two
devices differ only in the serial interface.
• MCP23017 – I
2
C interface
• MCP23S17 – SPI interface
The MCP23X17 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits (IODIRA/B).
The data for each input or output is kept in the
corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity
Inversion register. All registers can be read by the
system master.
The 16-bit I/O port functionally consists of two 8-bit
ports (PORTA and PORTB). The MCP23X17 can be
configured to operate in the 8-bit or 16-bit modes via
IOCON.BANK.
There are two interrupt pins, INTA and INTB, that can
be associated with their respective ports, or can be
logically OR’ed together so that both pins will activate if
either port causes an interrupt.
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1.
When any input state differs from its
corresponding Input Port register state. This is
used to indicate to the system master that an
input state has changed.
When an input state differs from a preconfigured
register value (DEFVAL register).
2.
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pins are used to determine the
device address.
©
2007 Microchip Technology Inc.
DS21952B-page 3
MCP23017/MCP23S17
1.1
Pin Descriptions
PINOUT DESCRIPTION
PDIP/
SOIC/
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
QFN
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
P
I
I
I/O
O
I
I
I
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Power
Ground
NC (MCP23017), Chip Select (MCP23S17)
Serial clock input
Serial data I/O (MCP23017), Serial data input (MCP23S17)
NC (MCP23017), Serial data out (MCP23S17)
Hardware address pin. Must be externally biased.
Hardware address pin. Must be externally biased.
Hardware address pin. Must be externally biased.
Hardware reset. Must be externally biased.
Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up
resistor.
TABLE 1-1:
Pin
Name
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
V
DD
V
SS
NC/CS
SCL/SCK
SDA/SI
NC/SO
A0
A1
A2
RESET
INTB
INTA
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
DS21952B-page 4
©
2007 Microchip Technology Inc.
MCP23017/MCP23S17
1.2
Power-on Reset (POR)
1.3.1
The on-chip POR circuit holds the device in reset until
V
DD
has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum V
DD
rise time is specified in
Section 2.0
“Electrical Characteristics”.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
BYTE MODE AND SEQUENTIAL
MODE
The MCP23X17 family has the ability to operate in Byte
mode or Sequential mode (IOCON.SEQOP).
Byte Mode
disables automatic Address Pointer
incrementing. When operating in Byte mode, the
MCP23X17 family does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually access the
same address by providing extra clocks (without
additional control bytes). This is useful for polling the
GPIO register for data changes or for continually
writing to the output latches.
A special mode
(Byte mode with IOCON.BANK =
0)
causes the address pointer to toggle between
associated A/B register pairs. For example, if the BANK
bit is cleared and the Address Pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note that the
Address Pointer can initially point to either address in
the register pair.
Sequential mode
enables automatic address pointer
incrementing. When operating in Sequential mode, the
MCP23X17 family increments its address counter after
each byte during the data transfer. The Address Pointer
automatically rolls over to address 00h after accessing
the last register.
These two modes are not to be confused with single
writes/reads and continuous writes/reads that are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
perform a continuous read. In this case, the
MCP23X17 would not increment the Address Pointer
and would repeatedly drive data from the same
location.
1.3
Serial Interface
This block handles the functionality of the I
2
C
(MCP23017) or SPI (MCP23S17) interface protocol.
The MCP23X17 contains 22 individual registers (11
register pairs) that can be addressed through the Serial
Interface block, as shown in
Table 1-2.
TABLE 1-2:
REGISTER ADDRESSES
Access to:
IODIRA
IODIRB
IPOLA
IPOLB
GPINTENA
GPINTENB
DEFVALA
DEFVALB
INTCONA
INTCONB
IOCON
IOCON
GPPUA
GPPUB
INTFA
INTFB
INTCAPA
INTCAPB
GPIOA
GPIOB
OLATA
OLATB
Address
Address
IOCON.BANK =
1
IOCON.BANK =
0
00h
10h
01h
11h
02h
12h
03h
13h
04h
14h
05h
15h
06h
16h
07h
17h
08h
18h
09h
19h
0Ah
1Ah
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
1.3.2
1.3.2.1
I
2
C INTERFACE
I
2
C Write Operation
The I
2
C write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1.
This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23017. The operation is ended with a Stop (P)
or Restart (SR) condition being generated by the
master.
Data is written to the MCP23017 after every byte
transfer. If a Stop or Restart condition is generated
during a data transfer, the data will not be written to the
MCP23017.
Both “byte writes” and “sequential writes” are
supported by the MCP23017. If Sequential mode is
enabled (IOCON, SEQOP =
0)
(default), the
MCP23017 increments its address counter after each
ACK during the data transfer.
©
2007 Microchip Technology Inc.
DS21952B-page 5
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