AM29N323DT11AWKI datasheet, PDF

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AM29N323DT11AWKI: Description32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory; Categorystorage storage; File Size528KB，48 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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AM29N323DT11AWKI Overview

32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

AM29N323DT11AWKI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
package instruction	BGA, BGA47,8X14,40/20
Reach Compliance Code	unknow
Maximum access time	120 ns
startup block	TOP
command user interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B47
JESD-609 code	e0
memory density	33554432 bi
Memory IC Type	FLASH
memory width	16
Number of departments/size	8,63
Number of terminals	47
word count	2097152 words
character code	2000000
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA47,8X14,40/20
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	1.8 V
Certification status	Not Qualified
ready/busy	YES
Department size	4K,32K
Maximum standby current	0.00001 A
Maximum slew rate	0.06 mA
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
switch bit	YES
type	NOR TYPE

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Am29N323D

Data Sheet

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Publication Number

23476N

Revision

Amendment

Issue Date

August 8, 2002

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram of

Simultaneous Operation Circuit . . . . . . . . . . . . . . 5

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6

Special Handling Instructions for FBGA Package .................... 6

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations ......................................................9

DQ2: Toggle Bit II ................................................................... 23

Table 5. DQ6 and DQ2 Indications ................................................ 23

Reading Toggle Bits DQ6/DQ2 ............................................... 23

DQ5: Exceeded Timing Limits ................................................ 23

DQ3: Sector Erase Timer ....................................................... 24

Table 6. Write Operation Status ..................................................... 24

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25

Figure 5. Maximum Negative Overshoot Waveform ...................... 25

Figure 6. Maximum Positive Overshoot Waveform........................ 25

Requirements for Asynchronous Read Operation (Non-Burst) 9

Requirements for Synchronous (Burst) Read Operation .......... 9

Programmable Wait State ...................................................... 10

Power Saving Function ........................................................... 10

Simultaneous Read/Write Operations with Zero Latency ....... 10

Writing Commands/Command Sequences ............................ 10

Accelerated Program Operation ............................................. 11

Autoselect Functions .............................................................. 11

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Input ............................................. 11

Output Disable Mode .............................................................. 11

Hardware Data Protection ...................................................... 11

Low VCC Write Inhibit ............................................................ 12

Write Pulse “Glitch” Protection ............................................... 12

Logical Inhibit .......................................................................... 12

Table 2. Sector Address Table ........................................................13

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 7. Test Setup....................................................................... 27

Table 7. Test Specifications ........................................................... 27

Key to Switching Waveforms. . . . . . . . . . . . . . . . 27

Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. Input Waveforms and Measurement Levels ................... 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Synchronous/Burst Read ........................................................ 28

Figure 9. Burst Mode Read ............................................................ 28

Asynchronous Read ............................................................... 29

Figure 10. Asynchronous Mode Read............................................ 29

Figure 11. Reset Timings............................................................... 30

Erase/Program Operations ..................................................... 31

Figure 12. Program Operation Timings..........................................

Figure 13. Chip/Sector Erase Operations ......................................

Figure 14. Accelerated Unlock Bypass Programming Timing........

Figure 15. Data# Polling Timings (During Embedded Algorithm) ..

Figure 16. Toggle Bit Timings (During Embedded Algorithm)........

Figure 17. Latency with Boundary Crossing ..................................

Figure 18. Initial Access with Power Saving (PS)

Function and Address Boundary Latency ......................................

Figure 19. Initial Access with Address Boundary Latency .............

Figure 20. Example of Five Wait States Insertion ..........................

Figure 21. Back-to-Back Read/Write Cycle Timings ......................

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15

Reading Array Data ................................................................ 15

Set Wait State Command Sequence ...................................... 15

Table 3. Third Cycle Address/Data .................................................15

Enable PS (Power Saving) Mode Command Sequence ........ 15

Sector Lock/Unlock Command Sequence .............................. 15

Reset Command ..................................................................... 15

Autoselect Command Sequence ............................................ 16

Program Command Sequence ............................................... 16

Unlock Bypass Command Sequence ..................................... 16

Figure 1. Program Operation .......................................................... 17

Chip Erase Command Sequence ........................................... 18

Sector Erase Command Sequence ........................................ 18

Erase Suspend/Erase Resume Commands ........................... 19

Figure 2. Erase Operation............................................................... 19

Table 4. Command Definitions .......................................................20

Erase and Programming Performance . . . . . . . 41

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42

FDD047—47-Pin Fine-Pitch Ball Grid Array

(FBGA) 7 x 10 mm package ................................................... 42

Mask Set Revision . . . . . . . . . . . . . . . . . . . . . . . . 44

Appendix A: Daisy Chain Information . . . . . . . . 45

Table 8. Daisy Chain Part for 32Mbit 0.23 µm Flash Products

(FDD047, 7 x 10 mm) ..................................................................... 45

Table 9. FDD047 Package Information .......................................... 45

Table 10. FDD047 Connections ..................................................... 45

Figure 1. FDD047 Daisy Chain Layout

(Top View, Balls Facing Down) ...................................................... 45

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 21

DQ7: Data# Polling ................................................................. 21

Figure 3. Data# Polling Algorithm ................................................... 21

DQ6: Toggle Bit I .................................................................... 22

Figure 4. Toggle Bit Algorithm......................................................... 22

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

August 8, 2002

Am29N323D

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