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87946AYI-01LFT

Description
TQFP-32, Reel
Categorylogic   
File Size406KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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87946AYI-01LFT Overview

TQFP-32, Reel

87946AYI-01LFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTQFP
package instructionLQFP-32
Contacts32
Manufacturer packaging codePRG32
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
series87946
Input adjustmentDIFFERENTIAL
JESD-30 codeS-PQFP-G32
JESD-609 codee3
length7 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Maximum Frequency@Nom-Sup250000000 Hz
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals32
Actual output times10
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP32,.35SQ,32
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3,3.3 V
Maximum supply current (ICC)55 mA
propagation delay (tpd)3.8 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.13 ns
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width7 mm
Base Number Matches1
1-to-10 Low Skew,
1, 2
LVCMOS/LVTTL
2.5V, 3.3V Fanout Buffer
87946I-01
Datasheet
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
The 87946I-01 is a low skew, ÷1, ÷2 Fanout Buffer. The 87946I-01
has one LVPECL clock input pair. The PCLK/nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50 series or parallel
terminated transmission lines. The effective fanout can be increased
from 10 to 20 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of
each bank. The outputs can be utilized in the ÷1, ÷2 or a combination
of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the
internal frequency dividers and also controls the active and high
impedance states of all outputs.
The 87946I-01 is characterized at 3.3V core/3.3V output and 3.3V
core/2.5V output. Guaranteed bank, output and part-to-part skew
characteristics make the 87946I-01 ideal for those clock distribution
applications demanding well defined performance and repeatability.
Features
Ten single ended LVCMOS/LVTTL outputs,
7 typical output impedance
LVPECL clock input pair
PCLK/nPCLK supports the following input levels:
LVPECL, CML, SSTL
Maximum input frequency: 250MHz
Output skew: 120ps (maximum)
Part-to-part skew: 700ps (maximum)
Multiple frequency skew: 320ps (maximum)
Additive phase jitter, RMS: 0.19ps (typical)
3.3V core, 3.3V or 2.5V output supply modes-40°C to 85°C
ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement use 87946i-147
Pin Assignment
MR/nOE
GND
GND
V
DDA
V
DDA
QA0
QA1
QA2
Block Diagram
nc
PCLK
Pulldown
nPCLK
Pullup
÷1
÷2
DIV_SELA
Pulldown
0
1
DIV_SELB
Pulldown
0
1
DIV_SELC
Pulldown
MR/nOE
Pulldown
3
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
9
V
DDC
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
QC2
GND
GND
QC0
QC1
V
DDC
QC3
GND
QB0
V
DDB
QB1
GND
QB2
V
DDB
V
DDC
0
1
3
QA0:QA2
V
DD
PCLK
nPCLK
DIV_SELA
DIV_SELB
QB0:QB2
DIV_SELC
GND
4
QC0:QC3
87946I-01
32-Lead LQFP
7mm x 7mm x 1.45mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, September 20, 2016

87946AYI-01LFT Related Products

87946AYI-01LFT 87946AYI-01LF
Description TQFP-32, Reel TQFP-32, Tray
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TQFP TQFP
package instruction LQFP-32 LQFP-32
Contacts 32 32
Manufacturer packaging code PRG32 PRG32
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Is Samacsys N N
series 87946 87946
Input adjustment DIFFERENTIAL DIFFERENTIAL
JESD-30 code S-PQFP-G32 S-PQFP-G32
JESD-609 code e3 e3
length 7 mm 7 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Maximum Frequency@Nom-Sup 250000000 Hz 250000000 Hz
Humidity sensitivity level 3 3
Number of functions 1 1
Number of terminals 32 32
Actual output times 10 10
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Output characteristics 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP
Encapsulate equivalent code QFP32,.35SQ,32 QFP32,.35SQ,32
Package shape SQUARE SQUARE
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius) 260 260
power supply 2.5/3.3,3.3 V 2.5/3.3,3.3 V
Maximum supply current (ICC) 55 mA 55 mA
propagation delay (tpd) 3.8 ns 3.8 ns
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.13 ns 0.13 ns
Maximum seat height 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface MATTE TIN MATTE TIN
Terminal form GULL WING GULL WING
Terminal pitch 0.8 mm 0.8 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 7 mm 7 mm
Base Number Matches 1 1
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