DS1743/DS1743P
Y2K-Compliant, Nonvolatile Timekeeping
RAMs
FEATURES
Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM. These Registers Reside in
the Eight Top RAM Locations.
Century Byte Register
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
through 2099
Low-Battery-Voltage Level Indicator Flag
Power-Fail Write Protection Allows for ±10%
V
CC
Power-Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only
Standard JEDEC Bytewide 8k x 8 Static
RAM Pinout
PowerCap Module Board Only
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174XP Timekeeping RAM
Underwriters Laboratories (UL) Recognized
to Prevent Charging of the Internal Lithium
Battery
PIN CONFIGURATIONS
TOP VIEW
N.C.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
28
2
DS1743
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
V
CC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
28-Pin Encapsulated Package
(28 PIN 740)
N.C.
N.C.
N.C.
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DS1743P
X1
GND
V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
N.C.
N.C.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-Pin PowerCap Module Board
(Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may
be simultaneously available through various sales channels. For information about device errata, click here:
www.maximintegrated.com/errata.
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19-6719; Rev 9/13
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
PIN
PDIP
PowerCap
1, 2, 3,
1
31–34
2
30
3
25
4
24
5
23
6
22
7
21
8
20
9
19
10
18
11
16
12
15
13
14
14
17
15
13
16
12
17
11
18
10
19
9
NAME
N.C.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
DQ3
DQ4
DQ5
DQ6
DQ7
FUNCTION
No Connection
PIN
PDIP
PowerCap
20
21
22
23
24
25
26
27
Data Input/
Output
Ground
—
Data Input/
Output
—
X1, X2
V
BAT
28
—
8
28
7
29
27
26
—
6
5
4
NAME
CE
A10
OE
A11
A9
A8
CE2
WE
V
CC
RST
FUNCTION
Chip Enable,
Active Low
Address Input
Output Enable,
Active Low
Address Input
Chip Enable 2
Write Enable,
Active Low
Power-Supply
Input
Power-On Reset
Output, Active
Low
Crystal
Connection
Battery
Connection
Address Input
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DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
PART
DS1743-85+
DS1743-100+
DS1743-100 IND+
DS1743P-85+
DS1743P-100+
DS1743P-100IND+
DS1743W-120+
DS1743W-120 IND+
DS1743W-150+
DS1743W-150 IND+
DS1743WP-120+
DS1743WP-120 IND+
DS9034PCX+
DS9034I-PCX+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
28 EDIP Module
28 EDIP Module
28 EDIP Module
34 PowerCap*
34 PowerCap*
34 PowerCap*
28 EDIP Module
28 EDIP Module
28 EDIP Module
28 EDIP Module
34 PowerCap*
34 PowerCap*
PowerCap
PowerCap IND
VOLTAGE
(V)
5
5
5
5
5
5
3.3
3.3
3.3
3.3
3.3
3.3
—
—
TOP MARK**
DS1743-85
DS1743-100
DS1743-100-IND
DS1743P-85
DS1743P-100
DS1743P-100 IND
DS1743W-120
DS1743W-120 IND
DS1743W-150
DS1743W-150 IND
DS1743WP-120
DS1743WP-120 IND
DS9034PC
DS9034PCI
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*DS9034PCX+
or DS9034I-PCX+ required (must be ordered separately).
**A ‘+’ indicates lead(Pb)-free. The top mark will include a ‘+’ symbol on lead(Pb)-free devices.
DESCRIPTION
The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM
locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in
24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur
during clock update cycles. The double-buffered system also prevents time loss as the timekeeping
countdown continues unabated by access to time register data. The DS1743 also contains its own power-
fail circuitry, which deselects the device when the V
CC
supply is in an out-of-tolerance condition. When
V
CC
is above V
PF
, the device is fully accessible. When V
CC
is below V
PF
, the internal
CE
signal is forced
high, preventing any access. When V
CC
rises above V
PF
, access remains inhibited for T
REC
, allowing time
for the system to stabilize. These features prevent loss of data from unpredictable system operation brought
on by low V
CC
as errant access and update cycles are avoided.
PACKAGES
The DS1743 is available in two packages: the 28-pin DIP and the 34-pin PowerCap module. The 28-pin
DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1743P after the completion of the surface-mount process. Mounting the PowerCap after the surface-
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers.
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DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the
RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The
contents of the time and date registers are in the BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register
updating process has been re-enabled. Updating is within a second after the read bit is written to 0.
The READ bit must be a zero for a minimum of 500µs to ensure the external registers are updated.
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DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
Dallas
Semiconductor
DS1743
Table 1. Truth Table
CE
V
CC
V
IH
X
V
CC
> V
PF
V
IL
V
IL
V
IL
V
SO
< V
CC
< V
PF
X
V
CC
<V
SO
<V
PF
X
CE2
X
V
IL
V
IH
V
IH
V
IH
X
X
OE
X
X
X
V
IL
V
IH
X
X
WE
X
X
V
IL
V
IH
V
IH
X
X
MODE
Deselect
Deselect
Write
Read
Read
Deselect
Deselect
DQ
High-Z
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
POWER
Standby
Standby
Active
Active
Active
CMOS Standby
Data-Retention
Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates
to the DS1743 registers. The user can subsequently load correct date and time values into all eight
registers, followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new
settings into the clock, allowing timekeeping operations to resume from the new set-point.
Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts
updates to the DS1743 registers. The user can subsequently read the date and time values from the eight
registers without those contents possibly changing during those I/O operations. A subsequent write cycle
of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the previous
set-point.
The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a
write cycle to Control if either the W or R bits are being set to 1 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write cycle
to Control if the W bit is being cleared to 0 in that write operation.
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