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PLL620-20

Description
Low Phase Noise XO (for HF Fund. and 3rd O.T.)
File Size196KB,7 Pages
ManufacturerPLL (PhaseLink Corporation)
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PLL620-20 Overview

Low Phase Noise XO (for HF Fund. and 3rd O.T.)

PLL620-20
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
FEATURES
100MHz to 200MHz Fund. or 3
rd
OT Crystal.
Output range: 100 – 200MHz (no multiplication).
Available outputs: PECL, or LVDS.
OESEL/OECTRL for both PECL & LVDS.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Die thickness 10 mil.
DIE CONFIGURATION
65 mil
Reserved
Reserved
VDD
VDD
VDD
VDD
N/C
N/C
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
N/C
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OUTSEL^
XIN
XOUT
N/C
62 mil
26
27
Die ID:
A1212-12
15
28
14
N/C
OE
CTRL
N/C
13
29
12
11
30
DESCRIPTION
The PLL620-20 is an XO IC specifically designed to
work with high frequency fundamental and third
overtone crystals. Its design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. It
achieves very low current into the crystal resulting in
better overall stability. It is ideal for XO applications
requiring LVDS or PECL output levels at high
frequencies.
C502A
31
1
2
3
4
5
6
7
8
10
9
Reserved
Y
(0,0)
X
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
Selected Output
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
0
1
LVDS
PECL (default)
BLOCK DIAGRAM
Pad #9
OUTSEL
Pad #30
OE_CTRL
0
1
OE
X+
X-
Oscillator
Amplifier
0
1
0
1
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
Q
Q
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OUTSEL is “1”
Logical states defined by CMOS levels if OUTSEL is “0”
PLL620-20
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
GNDBUF
State
GNDBUF
GND
GND
GND
GND
GND

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