Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9271
FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise = 1.1 nV/√Hz @ 5 MHz typical,
gain = 18 dB
SPI-programmable gain = 14 dB/15.6 dB/18 dB
Single-ended input; V
IN
maximum = 400 mV p-p/
333 mV p-p/250 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 70 MHz
Full-scale (FS) output = 2 V p-p differential
Variable gain amplifier (VGA)
Gain range = −6 dB to +24 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
3
rd
-order Butterworth cutoff
Programmable from 8 MHz to 18 MHz
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 50 MSPS
SNR = 70 dB
SFDR = 80 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes crosspoint switch to support
continuous wave (CW) Doppler
Low power, 150 mW per channel at 12 bits/40 MSPS (TGC)
90 mW per channel in CW Doppler
Single 1.8 V supply (3.3 V supply for CW Doppler output bias)
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP
FUNCTIONAL BLOCK DIAGRAM
DRVDD
PDWN
STBY
AVDD
LOSW-A
LO-A
LI-A
LG-A
LOSW-B
LO-B
LI-B
LG-B
LOSW-C
LO-C
LI-C
LG-C
LOSW-D
LO-D
LI-D
LG-D
LOSW-E
LO-E
LI-E
LG-E
LOSW-F
LO-F
LI-F
LG-F
LOSW-G
LO-G
LI-G
LG-G
LOSW-H
LO-H
LI-H
LG-H
AD9271
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTA+
DOUTA–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTB+
DOUTB–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTC+
DOUTC–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTD+
DOUTD–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTE+
DOUTE–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTF+
DOUTF–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTG+
DOUTG–
LNA
VGA
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTH+
DOUTH–
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
REFERENCE
SWITCH
ARRAY
GAIN–
SENSE
VREF
REFB
REFT
RBIAS
GAIN+
CSB
SCLK
SDIO
CWVDD
The AD9271 is designed for low cost, low power, small size,
and ease of use. It contains eight channels of a variable gain amp-
lifier (VGA) with low noise preamplifier (LNA); an antialiasing
filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-digital
converter (ADC).
Each channel features a variable gain range of 30 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 40 dB, and an ADC with a conversion
rate of up to 50 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input noise is typically 1.2 nV/√Hz,
and the combined input-referred noise of the entire channel
is 1.4 nV/√Hz at maximum gain. Assuming a 15 MHz noise
bandwidth (NBW) and a 15.6 dB LNA gain, the input SNR is
roughly 86 dB. In CW Doppler mode, the LNA output drives a
transconductance amp that is switched through an 8 × 6
differential crosspoint switch. The switch is programmable
through the SPI.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
06304-001
GENERAL DESCRIPTION
CWD[5:0]+/–
CLK+
CLK–
AD9271
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
ADC Timing Diagrams ............................................................... 9
Absolute Maximum Ratings.......................................................... 10
Thermal Impedance ................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Equivalent Circuits ......................................................................... 14
Typical Performance Characteristics ........................................... 16
Theory of Operation ...................................................................... 20
Ultrasound................................................................................... 20
Channel Overview...................................................................... 21
Input Overdrive .......................................................................... 23
CW Doppler Operation ............................................................. 24
TGC Operation ........................................................................... 25
ADC ............................................................................................. 27
Clock Input Considerations ...................................................... 28
Serial Port Interface (SPI) .............................................................. 35
Hardware Interface..................................................................... 35
Memory Map .................................................................................. 37
Reading the Memory Map Table .............................................. 37
Reserved Locations .................................................................... 37
Default Values ............................................................................. 37
Logic Levels ................................................................................. 37
Applications Information .............................................................. 41
Design Guidelines ...................................................................... 41
Evaluation Board ............................................................................ 42
Power Supplies ............................................................................ 42
Input Signals................................................................................ 42
Output Signals ............................................................................ 42
Default Operation and Jumper Selection Settings ................. 43
Quick Start Procedure ............................................................... 44
Schematics and Artwork ........................................................... 45
Outline Dimensions ....................................................................... 58
Ordering Guide .......................................................................... 58
REVISION HISTORY
5/09—Rev. A to Rev. B
Changes to Figure 27 ...................................................................... 17
Changes to Figure 40 and Figure 41 ............................................. 21
Changes to Ordering Guide .......................................................... 58
12/07—Rev. 0 to Rev. A
Change to AC Specifications Text .................................................. 4
Added Input Noise Current ............................................................ 4
Added Noise Figure .......................................................................... 4
Changes to Signal-to-Noise Ratio Units ........................................ 4
Changes to Harmonic Distortion Units ........................................ 5
Added Endnote 3 .............................................................................. 6
Changes to Table 6 .......................................................................... 11
Inserted Figure 19 and Figure 21 .................................................. 16
Changes to Figure 20 ...................................................................... 16
Changes to Theory of Operation Section .................................... 20
Changes to Figure 40 and Figure 41 ............................................. 21
Change to Active Impedance Matching Section ........................ 22
Changes to LNA Noise Section .................................................... 22
Changes to Figure 43...................................................................... 22
Change to Input Overload Protection Section ........................... 23
Changes to TGC Operation Section ............................................ 25
Changes to Gain Control Section ................................................. 26
Changes to Figure 52...................................................................... 26
Change to Table 11 ......................................................................... 33
Changes to Serial Interface Port (SPI) Section ........................... 35
Changes to Hardware Interface Section ...................................... 35
Changes to Reading the Memory Map Table Section ............... 37
Added Applications Information and
Design Guidelines Sections ...................................................... 41
Change to Input Signals Section................................................... 42
Changes to Figure 73...................................................................... 42
Changes to Table 16 ....................................................................... 55
6/07—Revision 0: Initial Version
Rev. B | Page 2 of
60
AD9271
The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many
applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO±) for
capturing data on the output and a frame clock (FCO±) trigger
for signaling a new output byte are provided.
Powering down individual channels is supported to increase
battery life for portable applications. There is also a standby
mode option that allows quick power-up for power cycling. In CW
Doppler operation, the VGA, AAF, and ADC are powered down.
The power of the TGC path scales with selectable speed grades.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in
pseudorandom patterns, and custom user-defined test patterns
entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9271 is
available in a 16 mm × 16 mm, RoHS compliant, 100-lead
TQFP. It is specified over the industrial temperature range of
−40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
Small Footprint. Eight channels are contained in a small,
space-saving package. Full TGC path, ADC, and crosspoint
switch contained within a 100-lead, 16 mm × 16 mm TQFP.
Low Power of 150 mW per Channel at 40 MSPS.
Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW
Doppler mode.
Ease of Use. A data clock output (DCO±) operates up to
300 MHz and supports double data rate (DDR) operation.
User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
Integrated Third-Order Antialiasing Filter. This filter is placed
between the TGC path and the ADC and is programmable
from 8 MHz to 18 MHz.
2.
3.
4.
5.
6.
Rev. B | Page 3 of
60
AD9271
SPECIFICATIONS
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, f
IN
= 5 MHz, R
S
= 50 Ω, LNA gain = 15.6 dB (6), AAF
LPF cutoff = 1/3 × f
S
, HPF cutoff = 700 kHz, full temperature, unless otherwise noted.
Table 1.
Parameter
LNA CHARACTERISTICS
Gain = 5/6/8
1
Conditions
Single-ended input
to differential output
Single-ended input
to single-ended
output
LNA output limited
to 2 V p-p differential
output
Min
AD9271-25
Typ
14/15.6/18
8/9.6/12
Max
Min
AD9271-40
Typ
14/15.6/18
8/9.6/12
Max
Min
AD9271-50
Typ
14/15.6/18
8/9.6/12
Max
Unit
dB
dB
Input Voltage Range,
Gain = 5/6/8
Input Common
Mode
Input Resistance
400/333/250
400/333/250
400/333/250
mV p-p
SE
2
V
Ω
Ω
kΩ
pF
MHz
pA/√Hz
nV/√Hz
mV p-p
1.4
RFB = 200 Ω
RFB = 400 Ω
RFB = ∞
LI-x
50
100
15
15
40
1.1
1.4/1.4/1.3
770/650/495
1.4
50
100
15
15
60
1.1
1.3/1.2/1.1
770/650/495
1.4
50
100
15
15
70
1.1
1.3/1.2/1.1
770/650/495
Input Capacitance
−3 dB Bandwidth
Input Noise Current,
Gain = 5/6/8
Input Noise Voltage,
Gain = 5/6/8
1 dB Input
Compression
Point, Gain = 5/6/8
Noise Figure
Active Termination
Match
Unterminated
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF High-Pass Cutoff
AAF Low-Pass Cutoff
Bandwidth Tolerance
Group Delay Variation
Input-Referred Noise
Voltage
Correlated Noise Ratio
Output Offset
Signal-to-Noise Ratio
(SNR)
f
IN
= 5 MHz
at −7 dBFS
f
IN
= 5 MHz
at −1 dBFS
R
S
= 0 Ω, RFB = ∞
V
GAIN
= 0 V
R
S
= 50 Ω, RFB = 200 Ω
RFB = ∞
6.7
4.9
6.7
4.4
6.7
4.2
dB
dB
−3 dB
−3 dB, programmable
f = 1 to 18 MHz,
gain = 0 V to 1 V
LNA gain = 5/6/8,
RFB = ∞
No signal, correlated/
uncorrelated
AAF high pass =
700 kHz
DC/350/700
1/3 × f
SAMPLE
(8 to 18)
±15
±2
1.7/1.6/1.5
−30
−50
+50
−35
DC/350/700
1/3 × f
SAMPLE
(8 to 18)
±15
±2
1.6/1.4/1.3
−30
+35
−35
DC/350/700
1/3 × f
SAMPLE
(8 to 18)
±15
±2
1.6/1.4/1.2
−30
+35
kHz
MHz
%
ns
nV/√Hz
dB
LSB
V
GAIN
= 0 V
V
GAIN
= 1 V
65.8
62
64.4
59.7
63.7
59
dBFS
dBFS
Rev. B | Page 4 of
60
AD9271
Parameter
Harmonic Distortion
Second Harmonic
f
IN
= 5 MHz
at −7 dBFS
Second Harmonic
f
IN
= 5 MHz
at −1 dBFS
Third Harmonic
f
IN
= 5 MHz
at −7 dBFS
Third Harmonic
f
IN
= 5 MHz
at −1 dBFS
Two-Tone IMD3
(2 × F1 − F2)
Distortion
f
IN1
= 5.0 MHz
at −7 dBFS,
f
IN2
= 6.0 MHz
at −7 dBFS
Channel-to-Channel
Crosstalk
Channel-to-Channel
Crosstalk (Over-
range Condition)
3
Overload Recovery
1
Conditions
V
GAIN
= 0 V
Min
AD9271-25
Typ
−73
Max
Min
AD9271-40
Typ
−71
Max
Min
AD9271-50
Typ
−71
Max
Unit
dBFS
V
GAIN
= 1 V
−80
−72
−68
dBFS
V
GAIN
= 0 V
−81
−77
−74
dBFS
V
GAIN
= 1 V
−65
−63
−66
dBFS
V
GAIN
= 1 V
−54.6
−63.4
−68.5
dBc
−70
−70
−70
−70
−70
−70
dB
dB
GAIN ACCURACY
Gain Law Confor-
mance Error
Full TGC path,
f
IN
= 1 MHz to 10 MHz,
gain = 0 V to 1 V
25°C
0 < V
GAIN
< 0.1 V
0.1 V < V
GAIN
< 0.9 V
0.9 V < V
GAIN
< 1 V
V
GAIN
= 0.5 V,
normalized for ideal
AAF loss
0.1 V < V
GAIN
< 0.9 V
−1.2
5
5
5
Degrees
+0.8
+1.2
−1.2
−1.3
+1.3
−1.3
−1.2
+0.8
+1.2
−1.2
+1.3
−1.3
−1.2
+0.8
+1.2
−1.2
+1.3
dB
dB
dB
dB
Linear Gain Error
Channel-to-Channel
Matching
GAIN CONTROL
INTERFACE
Normal Operating
Range
Gain Range
Scale Factor
Response Time
CW DOPPLER MODE
Transconductance
Common Mode
Input-Referred Noise
Voltage
Output DC Bias
Maximum Output
Swing
0.2
0.2
0.2
dB
0
0 V to 1 V, normalized
for ideal AAF loss
30 dB change
LNA gain = 5/6/8
CW Doppler
output pins
LNA gain = 5/6/8,
R
S
= 0 Ω, RFB = ∞
Per channel
Per channel
10 to 40
31.6
350
10/12/16
1.5
1.8 /1.7/1.5
2.4
±2
1
0
10 to 40
31.6
350
10/12/16
1
0
10 to 40
31.6
350
10/12/16
1
V
dB
dB/V
ns
mA/V
V
nV/√Hz
mA
mA p-p
3.6
1.5
1.7 /1.5/1.4
2.4
±2
3.6
1.5
1.7 /1.5/1.3
2.4
±2
3.6
Rev. B | Page 5 of
60
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