M76DW52003TA
M76DW52003BA
32Mbit (4Mb x8/ 2Mb x16, Dual Bank, Boot Block) Flash Memory
and 4Mbit (256Kb x16) SRAM, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY
■
MULTIPLE MEMORY PRODUCT
– 32 Mbit (4Mb x8 or 2Mb x16), Dual Bank, Boot
Block, Flash Memory
– 4 Mbit (256Kb x 16) SRAM
■
SUPPLY VOLTAGE
– V
CCF
= 2.7V to 3.3V
– V
CCS
= 2.7V to 3.3V
– V
PPF
= 12V for Fast Program (optional)
■
■
■
Figure 1. Package
FBGA
ACCESS TIME: 70, 90ns
LOW POWER CONSUMPTION
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code, M76DW52003TA: 225Eh
– Bottom Device Code, M76DW52003BA:
225Fh
LFBGA73 (ZA)
8 x 11.6 mm
FLASH MEMORY
■
PROGRAMMING TIME
– 10µs per Byte/Word typical
– Double Word/ Quadruple Byte Program
■
■
EXTENDED MEMORY BLOCK
– Extra block used as security block or to store
additional information
MEMORY BLOCKS
– Dual Bank Memory Array: 8Mbit+24Mbit
– Parameter Blocks (Top or Bottom Location)
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
DUAL OPERATIONS
– Read in one bank while Program or Erase in
other
SRAM
■
4 Mbit (256Kb x 16)
■
■
■
ACCESS TIME: 70ns
LOW V
CCS
DATA RETENTION: 1.5V
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
■
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
V
PP
/WP PIN for FAST PROGRAM and WRITE
PROTECT
TEMPORARY BLOCK UNPROTECTION
MODE
COMMON FLASH INTERFACE
– 64 bit Security Code
■
■
■
September 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M76DW52003TA, M76DW52003BA
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
PP/
Write Protect (V
PP/
WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Reset/Block Temporary Unprotect (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
CCF
Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
CCS
Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
SS
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operation Modes, BYTE = VIH(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read . . . . . . . . . . . . . . . . . . . . . . .
Write . . . . . . . . . . . . . . . . . . . . . . .
Standby/Power-Down . . . . . . . . . .
Data Retention. . . . . . . . . . . . . . . .
Output Disable . . . . . . . . . . . . . . . .
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. . . . 11
. . . . 11
. . . . 11
. . . . 11
. . . . 11
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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M76DW52003TA, M76DW52003BA
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. SRAM Read AC Waveforms, G Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. SRAM Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. SRAM Write AC Waveforms, W Controlled with G Low . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . . 20
Table 9. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. SRAM Low V
CCS
Data Retention AC Waveforms, E1
S
or UB
S
/ LB
S
Controlled. . . . . . 22
Table 10. SRAM Low V
CCS
Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline
23
Table 11. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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M76DW52003TA, M76DW52003BA
SUMMARY DESCRIPTION
The M76DW52003TA and M76DW52003BA are
low voltage Multiple Memory Products that com-
bine two memory devices; a 32 Mbit Dual Bank,
boot block Flash memory (M29DW323D(T/B)) and
a 4Mbit SRAM. This document should be read in
conjunction with the M29DW323D datasheet.
Recommended operating conditions do not allow
both the Flash and SRAM devices to be active at
the same time.
The memory is offered in an LFBGA73
(8 x 11.6mm, 0.8 mm pitch) package and is sup-
plied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
V
CCF
Flash Power Supply
V
PP
/Write Protect
Ground
SRAM Power Supply
SRAM Ground
Not Connected Internally
Table 1. Signal Names
A0-A17
A18-A20
DQ0-DQ7
DQ8-DQ14
DQ15A–1
G
W
Address Inputs common to the Flash
Memory and SRAM
Address Inputs for Flash Memory only
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Output Enable Input
Write Enable Input
V
PP
/WP
V
CCF
21
A0-A20
E
F
G
W
RP
F
BYTE
E1
S
E2
S
UB
S
LB
S
M76DW52003TA
M76DW52003BA
15
DQ0-DQ14
DQ15A–1
V
CCS
V
PP
/WP
V
SS
V
CCS
V
SSS
NC
Flash Memory Control Functions
E
F
RP
F
Chip Enable Input
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
RB
RB
BYTE
SRAM Control Functions
E1
S
, E2
S
UB
S
LB
S
Chip Enable Inputs
Upper Byte Enable Input
Lower Byte Enable Input
V
SS
AI08712
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M76DW52003TA, M76DW52003BA
Figure 3. LFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
NC
NC
B
NC
NC
NC
NC
C
NC
A7
LBS
VPP
/WP
W
A8
A11
D
A3
A6
UBS
RPF
E2S
A19
A12
A15
E
A2
A5
A18
RB
A20
A9
A13
NC
F
NC
A1
A4
A17
A10
A14
NC
NC
G
NC
A0
VSS
DQ1
DQ6
NC
A16
NC
H
EF
G
DQ9
DQ3
DQ4
DQ13
DQ15
/A-1
BYTE
J
E1S
DQ0
DQ10
VCCF
VCCS
DQ12
DQ7
VSS
K
DQ8
DQ2
DQ11
NC
DQ5
DQ14
M
NC
NC
NC
NC
N
NC
NC
AI08713
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