SSTUH32864
1.8 V high output drive configurable registered buffer for
DDR2 RDIMM applications
Rev. 01 — 22 April 2005
Product data sheet
1. General description
The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed
for 1.7 V to 1.9 V V
DD
operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUH32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and un-driven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs
must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUH32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.
The SSTUH32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)
package.
Philips Semiconductors
SSTUH32864
1.8 V high output drive DDR registered buffer
The SSTUH32864 is identical to SSTU32864 in function and performance, with
higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while
maintaining speed and signal integrity.
2. Features
s
Configurable register supporting DDR2 Registered DIMM applications
s
Higher output drive strength version of SSTU32864 optimized for high-capacitive load
nets
s
Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
s
Controlled output impedance drivers enable optimal signal integrity and speed
s
Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
s
Supports up to 450 MHz clock frequency of operation
s
Optimized pinout for high-density DDR2 module design
s
Chip-selects minimize power consumption by gating data outputs from changing state
s
Supports SSTL_18 data inputs
s
Differential clock (CK and CK) inputs
s
Supports LVCMOS switching levels on the control and RESET inputs
s
Single 1.8 V supply operation
s
Available in 96-ball, 13.5
×
5.5 mm, 0.8 mm ball pitch LFBGA package
3. Ordering information
Table 1:
Ordering information
T
amb
= 0
°
C to +70
°
C.
Type number
SSTUH32864EC/G
SSTUH32864EC
Solder process
Package
Name
Pb-free (SnAgCu
LFBGA96
solder ball compound)
SnPb solder ball
compound
LFBGA96
Description
Version
plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5
×
5.5
×
1.05 mm
plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5
×
5.5
×
1.05 mm
9397 750 14137
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2005
2 of 20
Recruitment
京公网安备 11010802033920号
EEWORLD
