SSTUH32864EC/G-T datasheet, PDF

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SSTUH32864EC/G-T: DescriptionRegister 1.8V config reg buffer/ddrii; Categorysemiconductor Other integrated circuit (IC); File Size112KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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SSTUH32864

1.8 V high output drive conﬁgurable registered buffer for

DDR2 RDIMM applications

Rev. 01 — 22 April 2005

Product data sheet

1. General description

The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer designed

for 1.7 V to 1.9 V V

operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTUH32864 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout conﬁguration of the 1 : 2 pinout from A conﬁguration

(when LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout

conﬁguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and un-driven (ﬂoating) data, clock and

reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all

registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs

must always be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUH32864 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from

changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is

LOW, the Qn outputs will function normally. The RESET input has priority over the DCS

and CSR control and will force the outputs LOW. If the DCS-control functionality is not

desired, then the CSR input can be hardwired to ground, in which case the setup time

requirement for DCS would be the same as for the other Dn data inputs.

The SSTUH32864 is available in a 96-ball, low proﬁle ﬁne-pitch ball grid array (LFBGA96)

package.

SSTUH32864EC/G-T Related Products

	SSTUH32864EC/G-T	SSTUH32864EC-S	SSTUH32864EC/G-S	SSTUH32864EC/G	SSTUH32864EC,557	SSTUH32864EC/G,557	SSTUH32864EC/G,551	SSTUH32864EC,551	SSTUH32864EC,518
Description	Register 1.8V config reg buffer/ddrii	Register 1.8V config reg buffer/ddrii	Buffer and line driver 1.8V config reg buffer/ddrii	Register 1.8V config reg buffer/ddrii	IC BUFFER 1.8V 1/14BIT SOT536-1	IC BUFFER 1.8V 1/14BIT SOT536-1	IC BUFFER 1.8V 1/14BIT SOT536-1	IC BUFFER 1.8V 1/14BIT SOT536-1	IC BUFFER 1.8V 1/14BIT SOT536-1
Maker	-	NXP	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Maximum operating temperature	-	+ 70 C	-	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Parts packaging code	-	-	-	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	-	-	-	LFBGA, BGA96,6X16,32	LFBGA, BGA96,6X16,32	13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96	13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96	LFBGA,	LFBGA,
Contacts	-	-	-	96	96	96	96	96	96
Manufacturer packaging code	-	-	-	SOT-536-1	SOT536-1	SOT-536-1	SOT536-1	SOT536-1	SOT536-1
Reach Compliance Code	-	-	-	unknown	unknown	unknown	unknown	unknown	unknown
series	-	-	-	SSTU	SSTU	SSTU	SSTU	SSTU	SSTU
JESD-30 code	-	-	-	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96
length	-	-	-	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm
Logic integrated circuit type	-	-	-	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of digits	-	-	-	14	14	14	14	14	14
Number of functions	-	-	-	1	1	1	1	1	1
Number of terminals	-	-	-	96	96	96	96	96	96
Output characteristics	-	-	-	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN
Output polarity	-	-	-	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	-	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	-	-	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA
Package shape	-	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	-	-	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
propagation delay (tpd)	-	-	-	1.8 ns	1.8 ns	1.8 ns	1.8 ns	1.8 ns	1.8 ns
Certification status	-	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	-	-	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm
Maximum supply voltage (Vsup)	-	-	-	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	-	-	-	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	-	-	-	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	-	-	-	YES	YES	YES	YES	YES	YES
technology	-	-	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	-	-	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	-	-	-	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	-	-	-	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	-	-	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Trigger type	-	-	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	-	-	-	5.5 mm	5.5 mm	5.5 mm	5.5 mm	5.5 mm	5.5 mm
minfmax	-	-	-	450 MHz	450 MHz	450 MHz	450 MHz	450 MHz	450 MHz
Brand Name	-	-	-	-	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor

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