ICS343
Field Programmable Triple Output SS VersaClock Synthesizer
Description
The ICS343 is a low cost, triple-output, field program-
mable clock synthesizer. The ICS343 can generate
three output frequencies from 250 kHz to 200 MHz,
using up to three independently configurable PLLs.
The outputs may employ Spread Spectrum techniques
to reduce system electro-magnetic interference (EMI).
Using ICS’ VersaClock™ software to configure the PLL
and output, the ICS343 contains a One-Time Program-
mable (OTP) ROM to allow field programmability. Using
Phase-Locked Loop (PLL) techniques, the device runs
from a standard fundamental mode, inexpensive crys-
tal, or clock. It can replace multiple crystals and oscilla-
tors, saving board space and cost.
The device also has a power down feature that
tri-states the clock outputs and turns off the PLLs when
the PDTS pin is taken low.
The ICS343 is also available in factory-programmed
custom versions for high-volume applications.
Features
•
8-pin SOIC package
•
Highly accurate frequency generation
•
M/N Multiplier PLL: M = 1...2048, N = 1...1024
•
Output clock frequencies up to 200 MHz
•
Spread spectrum capability for lower system EMI
•
Center or Down Spread up to 4% total
•
Selectable 32 kHz or 120 kHz modulation
•
Input crystal frequency from 5 to 27 MHz
•
Input clock frequency from 2 to 50 MHz
•
Operating voltage of 3.3 V, using advanced, low
•
•
power CMOS process
For one output clock, use the ICS341. For two output
clocks, see the ICS342. For more than three outputs,
see the ICS345 or ICS348.
Available in Pb (lead) free packaging
Block Diagram
VDD
OTP ROM
with PLL
Divider
Values
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
External capacitors are
required with a crystal input.
CLK1
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
CLK2
CLK3
GND
PDTS (both outputs and PLL)
MDS 343 F
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 090704
tel (408) 297-1201
●
www.icst.com
ICS343
Field Programmable Triple Output SS VersaClock
Pin Assignment
X1/ I CLK
VDD
GND
CLK1
1
2
3
4
8
7
6
5
X2
PDTS
CLK2
CLK3
Output Clock Selection Table
CLK2
CLK2
CLK3
Output
User
User
User
Frequency
Configurable Configurable Configurable
Spread
User
User
User
Amount
Configurable Configurable Configurable
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1/ICLK
VDD
GND
CLK1
CLK3
CLK2
PDTS
X2
Pin
Type
XI
Power
Power
Output
Output
Output
Input
XO
Connect to +3.3 V.
Connect to ground.
Pin Description
Connect this pin to a crystal or external clock input.
Clock output. Weak internal pull-down when tri-state.
Clock output. Weak internal pull-down when tri-state.
Clock output. Weak internal pull-down when tri-state.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.
Connect this pin to a crystal, or float for clock input.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS343 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
MDS 343 F
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 090704
tel (408) 297-1201
●
www.icst.com
ICS343
Field Programmable Triple Output SS VersaClock
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS343. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
Spread Spectrum Modulation
The ICS343 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
frequencies; thus, lowering a system’s
electro-magnetic interference (EMI). The modulation
rate is the time from transitioning from a minimum
frequency to a maximum frequency and then back to
the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is
equal in the positive and negative directions. The
effective average frequency is equal to the target
frequency. In applications where the clock is driving a
component with a maximum frequency rating, down
spread should be applied. In this case, the maximum
frequency, including modulation, is the target
frequency. The effective average frequency is less than
the target frequency.
The ICS343 operates in both center spread and down
spread modes. For center spread, the frequency can
be modulated between +/- 0.125% to +/-2.0%. For
down spread, the frequency can be modulated
between -0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates,
if a common VCO frequency can be identified.
ICS343 Configuration Capabilities
The architecture of the ICS343 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS343 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
OutputFreq
REFFreq
-------------------------------------
-
OutputDivide
=
⋅
M
----
-
N
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user-friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to
the output clock frequency may occur at a variety of
rates. For applications requiring the driving of
“down-circuit” PLLs, Zero Delay Buffers, or those
adhering to PCI standards, the spread spectrum
modulation rate should be set to 30-33 kHz. For other
applications, a 120 kHz modulation option is available.
MDS 343 F
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 090704
tel (408) 297-1201
●
www.icst.com
ICS343
Field Programmable Triple Output SS VersaClock
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS343. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Junction Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD+ 0.5
VDD+ 0.5
150
260
125
Units
V
V
V
°C
°C
°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS343M)
Ambient Operating Temperature (ICS343MI)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.15
Typ.
Max.
+70
+85
Units
°C
°C
V
ms
+3.3
+3.45
4
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3V ±5%,
Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Symbol
VDD
Conditions
Configuration
Dependent - See
VersaClock
TM
Estimates
Min.
3.15
Typ.
3.3
Max.
3.45
Units
V
mA
Operating Supply Current
Input High Voltage
IDD
Three 33.3333 MHz
outputs, PDTS = 1, No
load
Note 1
PDTS = 0
VDD-0.5
14
mA
20
0.4
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
Input Low Voltage
V
IH
V
IL
V
IH
V
IL
ICLK
ICLK
µA
V
V
V
VDD/2-1
V
VDD/2+1
MDS 343 F
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 090704
tel (408) 297-1201
●
www.icst.com
ICS343
Field Programmable Triple Output SS VersaClock
Parameter
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
Internal Pull-up Resistor
Internal Pull-down Resistor
Input Capacitance
Symbol
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUP
R
PD
C
IN
Conditions
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12 mA
Min.
VDD-0.4
2.4
Typ.
Max.
Units
V
V
0.4
±70
20
V
mA
Ω
kΩ
kΩ
pF
PDTS pin
CLK output
Inputs
250
525
4
Note 1: Example with 25 MHz crystal input with three outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Power-up time
Symbol
F
IN
Conditions
Fundamental Crystal
Input Clock
Min.
5
2
0.25
Typ.
Max. Units
27
50
200
MHz
MHz
MHz
ns
ns
60
10
2
%
ms
ms
t
OR
t
OF
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
PLL lock time from
power-up, Note 3
PDTS goes high until
stable CLK output, Spread
Spectrum Off, Note 3
PDTS goes high until
stable CLK output, Spread
Spectrum On, Note 3
40
1
1
49-51
4
0.2
4
7
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Note 1: Measured with 15 pF load.
t
ja
Configuration Dependent
Deviation from Mean.
Configuration Dependent
50
+200
ps
ps
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK3 for each PLL powered up.
MDS 343 F
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 090704
tel (408) 297-1201
●
www.icst.com
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