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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1764
SWITCHING
DUAL N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The
µ
PA1764 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
PACKAGE DRAWING (Unit : mm)
8
5
1 : Source 1
2 : Gate 1
7, 8 : Drain 1
3 : Source 2
4 : Gate 2
5, 6 : Drain 2
6.0 ±0.3
4.4
+0.10
–0.05
FEATURES
•
Dual chip type
•
Low on-state resistance
R
DS(on)1
= 27 mΩ TYP. (V
GS
= 10 V, I
D
= 3.5 A)
R
DS(on)2
= 32 mΩ TYP. (V
GS
= 4.5 V, I
D
= 3.5 A)
R
DS(on)3
= 34 mΩ TYP. (V
GS
= 4.0 V, I
D
= 3.5 A)
•
Low input capacitance
C
iss
= 1300 pF TYP.
•
Built-in G-S protection diode
•
Small and surface mount package (Power SOP8)
1
4
5.37 MAX.
1.44
0.8
1.8 MAX.
0.15
0.05 MIN.
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
µ
PA1764G
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC) (T
C
= 25°C)
Drain Current (pulse)
Note1
Total Power Dissipation (1 unit)
Note2
Total Power Dissipation (2 unit)
Channel Temperature
Storage Temperature
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
Notes 1.
2.
3.
Remark
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
P
T
T
ch
T
stg
I
AS
E
AS
60
±20
±7
±28
1.7
2.0
150
–55 to + 150
7
98
V
V
A
A
W
W
°C
°C
A
mJ
Gate
Body
Diode
EQUIVALENT CIRCUIT
(1/2 Circuit)
Drain
PW
≤
10
µ
s, Duty cycle
≤
1%
2
T
A
= 25°C, Mounted on ceramic substrate of 1200 mm x 2.2 mm
Starting T
ch
= 25°C, V
DD
= 30 V, R
G
= 25
Ω,
V
GS
= 20
→
0 V
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Gate
Protection
Diode
Source
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G14329EJ2V0DS00 (2nd edition)
Date Published May 2001 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1999, 2001
Electronics Design Contest
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