ATMEGA32L-8AUR datasheet, PDF - EEWORLD Datasheet

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ATMEGA32L-8AUR: DescriptionIC MCU 8BIT 32KB FLASH 44TQFP; CategoryThe embedded processor and controller Microcontrollers and processors; File Size6MB，346 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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ATMEGA32L-8AUR Overview

IC MCU 8BIT 32KB FLASH 44TQFP

ATMEGA32L-8AUR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	9 weeks
Samacsys Description	8-bit Microcontrollers - MCU AVR 32K FLSH 2K SRAM 1KB EE-8MHz IND
Has ADC	YES
Address bus width
bit size	8
CPU series	AVR RISC
maximum clock frequency	8 MHz
DAC channel	YES
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G44
JESD-609 code	e3
length	10 mm
Humidity sensitivity level	3
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Encapsulate equivalent code	TQFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	2048
rom(word)	16384
ROM programmability	FLASH
Maximum seat height	1.2 mm
speed	8 MHz
Maximum slew rate	5 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

User Manual

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Features

•

High-performance, Low-power Atmel

AVR

8-bit Microcontroller

•

Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 × 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16MHz

– On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

– 32Kbytes of In-System Self-programmable Flash program memory

– 1024Bytes EEPROM

– 2Kbytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

Operating Voltages

– 2.7V - 5.5V for ATmega32L

– 4.5V - 5.5V for ATmega32

Speed Grades

– 0 - 8MHz for ATmega32L

– 0 - 16MHz for ATmega32

Power Consumption at 1MHz, 3V, 25°C

– Active: 1.1mA

– Idle Mode: 0.35mA

– Power-down Mode: < 1µA

•

8-bit

Microcontroller

with 32KBytes

In-System

Programmable

Flash

ATmega32

ATmega32L

•

2503Q–AVR–02/11

ATmega32(L)

The Atmel

AVR

AVR core combines a rich instruction set with 32 general purpose working reg-

isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruction executed in one clock cycle. The

resulting architecture is more code efficient while achieving throughputs up to ten times faster

than conventional CISC microcontrollers.

The ATmega32 provides the following features: 32Kbytes of In-System Programmable Flash

Program memory with Read-While-Write capabilities, 1024bytes EEPROM, 2Kbyte SRAM, 32

general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-

scan, On-chip Debugging support and programming, three flexible Timer/Counters with com-

pare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented

Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with

programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscil-

lator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops

the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters,

SPI port, and interrupt system to continue functioning. The Power-down mode saves the register

contents but freezes the Oscillator, disabling all other chip functions until the next External Inter-

rupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC

Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and

ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/reso-

nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up

combined with low-power consumption. In Extended Standby mode, both the main Oscillator

and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the Application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effec-

tive solution to many embedded control applications.

The Atmel AVR ATmega32 is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-

tors, and evaluation kits.

Pin Descriptions

VCC

GND

Port A (PA7..PA0)

Digital supply voltage.

Ground.

Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port A output buffers have sym-

metrical drive characteristics with both high sink and source capability. When pins PA0 to PA7

are used as inputs and are externally pulled low, they will source current if the internal pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

2503Q–AVR–02/11

ATmega32(L)

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega32 as listed on

page

57.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins

PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.

The TD0 pin is tri-stated unless TAP states that shift out data are entered.

Port C also serves the functions of the JTAG interface and other special features of the

ATmega32 as listed on

page 60.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega32 as listed on

page

62.

RESET

Reset Input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in

Table 15 on page

37.

Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally con-

nected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

through a low-pass filter.

AREF is the analog reference pin for the A/D Converter.

XTAL1

XTAL2

AVCC

AREF

2503Q–AVR–02/11

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