STP16NK60Z - STB16NK60Z-S
STW16NK60Z
N-CHANNEL 600V - 0.38
Ω
- 14 A TO-220 /I2SPAK/TO-247
Zener - Protecdet SuperMESH™ MOSFET
TARGET SPECIFICATION
Table 1: General Features
TYPE
STP16NK60Z
STB16NK60Z-S
STW16NK60Z
■
■
■
■
■
■
Figure 1: Package
I
D
14 A
14 A
14 A
Pw
190 W
190 W
190 W
3
1
2
V
DSS
600 V
600 V
600 V
R
DS(on)
< 0.42
Ω
< 0.42
Ω
< 0.42
Ω
3
12
TYPICAL R
DS
(on) = 0.38
Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
GATE CHARGE MINIMIZED
VERY LOW INTRINSIC CAPACITANCES
VERY GOOD MANUFACTURING
REPEATIBILITY
TO-220
I
2
SPAK
3
2
1
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS-
FETs including revolutionary MDmesh™ products.
TO-247
Figure 2: Internal Schematic Diagram
APPLICATIONS
■
HIGH CURRENT, HIGH SPEED SWITCHING
■
IDEAL FOR OFF-LINE POWER SUPPLIES
Table 2: Order Codes
SALES TYPE
STP16NK60Z
STB16NK60Z-S
STW16NK60Z
MARKING
P16NK60Z
B16NK60Z
W16NK60Z
PACKAGE
TO-220
I
2
SPAK
TO-247
PACKAGING
TUBE
TUBE
TUBE
Rev. 1
September 2005
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice
.
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STP16NK65Z - STB16NK65Z-S - STW16NK60Z
Table 3: Absolute Maximum ratings
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
( )
P
TOT
V
ESD(G-S)
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 kΩ)
Gate- source Voltage
Drain Current (continuous) at T
C
= 25°C
Drain Current (continuous) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
Gate source ESD (HBM-C= 100pF, R= 1.5KΩ)
) Pulse width limited by safe operating area
(1) I
SD
≤
14 A, di/dt
≤
200 A/µs, V
DD
≤
V
(BR)DSS
, T
j
≤
T
JMAX.
Value
600
600
± 30
14
8.8
56
190
1.51
6000
Unit
V
V
V
A
A
A
W
W/°C
V
Table 4: Thermal Data
TO-220/ I²SPAK
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
62.5
300
0.66
50
TO-247
Table 5: Avalanche Characteristics
Symbol
I
AR
E
AS
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Parameter
Gate-Source Breakdown
Voltage
Test Conditions
Igs=± 1mA (Open Drain)
Min.
30
Max Value
14
360
Unit
A
mJ
Table 6: GATE-SOURCE ZENER DIODE
Symbol
BV
GSO
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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STP16NK60Z - STB16NK60Z-S - STW16NK60Z
ELECTRICAL CHARACTERISTICS
(T
CASE
=25°C UNLESS OTHERWISE SPECIFIED)
Table 7: On/Off
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
V
(BR)DSS
Parameter
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
Resistance
Drain-source
Breakdown Voltage
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Equivalent Output
Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
I
D
= 1 mA, V
GS
= 0
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 °C
V
GS
= ± 20V
V
DS
= V
GS
, I
D
= 100 µA
V
GS
= 10V, I
D
= 7 A
I
D
= 1 mA, V
GS
= 0
600
3
3.75
0.38
Min.
600
1
50
±10
4.5
0.42
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
V
Table 8: Dynamic
Symbol
g
fs
(1)
C
iss
C
oss
C
rss
C
oss eq.
(*)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Test Conditions
V
DS
= 15 V
,
I
D
= 7 A
V
DS
= 25V, f = 1 MHz, V
GS
= 0
Min.
Typ.
12
2650
285
62
158
30
25
70
15
86
17
46
Max.
Unit
S
pF
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
GS
= 0V, V
DS
= 0V to 480V
V
DD
= 480 V, I
D
= 14 A
R
G
= 4.7Ω V
GS
= 10 V
(Resistive Load see, Figure 3)
V
DD
= 480V, I
D
= 14 A,
V
GS
= 10V
(*) C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
Table 9: Source Drain Diode
Symbol
I
SD
I
SDM
(2)
V
SD
(1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
I
SD
I
SDM
(2)
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Source-drain Current
Source-drain Current (pulsed)
I
SD
= 14 A, V
GS
= 0
I
SD
= 14 A, di/dt = 100 A/µs
V
DD
= 100 V, T
j
= 25°C
(see test circuit, Figure 5)
I
SD
= 14 A, di/dt = 100 A/µs
V
DD
= 100 V, T
j
= 150°C
(see test circuit, Figure 5)
490
5.4
22
585
7
24
14
56
Test Conditions
Min.
Typ.
Max.
14
56
1.6
Unit
A
A
V
ns
µC
A
ns
µC
A
A
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
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STP16NK65Z - STB16NK65Z-S - STW16NK60Z
Figure 3: Unclamped Inductive Load Test Cir-
cuit
Figure 6: Unclamped Inductive Wafeform
Figure 4: Switching Times Test Circuit For Re-
sistive Load
Figure 7: Gate Charge Test Circuit
Figure 5: Test Circuit For Inductive Load
Switching and Diode Recovery Times
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STP16NK60Z - STB16NK60Z-S - STW16NK60Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com
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