TC74AC174P/F/FN/FT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74AC174P,TC74AC174F,TC74AC174FN,TC74AC174FT
Hex D-Type Flip Flop with Clear
The TC74AC174 is an advanced high speed CMOS HEX
D-TYPE FLIP FLOP fabricated with silicon gate and
double-layer metal wiring C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
Information signals applied to D inputs are transferred to the
Q output on the positive going edge of the clock pulse.
When the
CLR
input is held low, the Q output are in the low
logic level independent of the other inputs.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC174P
TC74AC174F
Features
•
•
•
•
High speed: f
max
= 180 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 8
μA
(max) at Ta = 25°C
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
Symmetrical output impedance: |I
OH
| = I
OL
= 24 mA (min)
Capability of driving 50
Ω
transmission lines.
Balanced propagation delays: t
pLH
∼
t
pHL
−
Wide operating voltage range: V
CC (opr)
= 2 to 5.5 V
Pin and function compatible with 74F174
TC74AC174FN
•
•
•
TC74AC174FT
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
1
2007-10-01
TC74AC174P/F/FN/FT
Pin Assignment
IEC Logic Symbol
(1)
(9)
(3)
(4)
(6)
(11)
(13)
(14)
CLR
Q1
D1
D2
Q2
D3
Q3
GND
1
2
3
4
5
6
7
8
(top view)
16
15
14
13
12
11
10
9
V
CC
Q6
D6
D5
Q5
D4
Q4
CK
CLR
CK
D1
D2
D3
D4
D5
D6
R
C1
1D
(2)
(5)
(7)
(10)
(12)
(15)
Q1
Q2
Q3
Q4
Q5
Q6
Truth Table
Inputs
CLR
Output
CK
X
Q
L
L
H
Q
n
D
X
L
H
X
Function
Clear
―
―
No Change
L
H
H
H
X: Don’t care
System Diagram
D1
3
D R
D2
4
D R
D3
6
D R
D4
11
D R
D5
13
D R
D6
14
D R
CLR
1
CK
CK
Q
CK
Q
CK
Q
CK
Q
CK
Q
CK
Q
9
2
Q1
5
Q2
7
Q3
10
Q4
12
Q5
15
Q6
2
2007-10-01
TC74AC174P/F/FN/FT
Absolute Maximum Ratings (Note 1)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−0.5
to 7.0
−0.5
to V
CC
+ 0.5
−0.5
to V
CC
+ 0.5
±20
±50
±50
±150
500 (DIP) (Note 2)/180 (SOP/TSSOP)
−65
to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta =
−40
to 65°C. From Ta = 65 to 85°C a derating factor of
−10
mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall time
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dV
Rating
2.0 to 5.5
0 to V
CC
0 to V
CC
−40
to 85
0 to 100 (V
CC
= 3.3 ± 0.3 V)
0 to 20 (V
CC
= 5 ± 0.5 V)
Unit
V
V
V
°C
ns/V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
3
2007-10-01
TC74AC174P/F/FN/FT
Electrical Characteristics
DC Characteristics
Ta = 25°C
Characteristics
Symbol
Test Condition
V
CC
(V)
2.0
High-level input
voltage
V
IH
―
3.0
5.5
2.0
Low-level input
voltage
V
IL
―
3.0
5.5
2.0
I
OH
=
−50 μA
High-level output
voltage
V
OH
V
IN
= V
IH
or
I
OH
=
−4
mA
V
IL
I
OH
=
−24
mA
I
OH
=
−75
mA
(Note)
3.0
4.5
3.0
4.5
5.5
2.0
I
OL
= 50
μA
Low-level output
voltage
V
OL
V
IN
= V
IH
or
I
OL
= 12 mA
V
IL
I
OL
= 24 mA
I
OL
= 75 mA
Input leakage
current
Quiescent supply
current
I
IN
I
CC
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND
(Note)
3.0
4.5
3.0
4.5
5.5
5.5
5.5
Min
1.50
2.10
3.85
―
―
―
1.9
2.9
4.4
2.58
3.94
―
―
―
―
―
―
―
―
―
Typ.
―
―
―
―
―
―
2.0
3.0
4.5
―
―
―
0.0
0.0
0.0
―
―
―
―
―
Max
―
―
―
0.50
0.90
1.65
―
―
―
―
―
―
0.1
0.1
0.1
0.36
0.36
―
±0.1
8.0
Ta =
−40
to 85°C
Min
1.50
2.10
3.85
―
―
―
1.9
2.9
4.4
2.48
3.80
3.85
―
―
―
―
―
―
―
―
Max
―
―
―
0.50
0.90
1.65
―
―
―
―
―
―
0.1
0.1
0.1
0.44
0.44
1.65
±1.0
80.0
μA
μA
V
V
V
V
Unit
Note:
This spec indicates the capability of driving 50
Ω
transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements
(input: t
r
= t
f
= 3 ns)
Characteristics
Symbol
Test Condition
V
CC
(V)
Minimum pulse width
(CK)
Minimum pulse width
( CLR )
Minimum set-up time
t
w (L)
t
w (H)
t
w (L)
―
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Ta =
25°C
Limit
7.0
5.0
7.0
5.0
7.0
4.0
1.0
1.0
6.0
3.5
Ta =
−40
to
85°C
Limit
7.0
5.0
7.0
5.0
7.0
4.0
1.0
1.0
6.0
3.5
ns
Unit
―
ns
t
s
―
ns
Minimum hold time
Minimum removal time
( CLR )
t
h
―
ns
t
rem
―
ns
4
2007-10-01
TC74AC174P/F/FN/FT
AC Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
input: t
r
= t
f
= 3 ns)
Characteristics
Propagation delay
time
(CK-Q)
Propagation delay
time
(
CLR
-Q)
Maximum clock
frequency
Input capacitance
Power dissipation
capacitance
f
max
C
IN
C
PD
―
―
(Note)
Symbol
Test Condition
V
CC
(V)
t
pLH
t
pHL
―
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Min
―
―
―
―
60
90
―
―
Ta = 25°C
Typ.
8.5
6.7
8.2
6.3
110
150
5
74
Max
14.4
9.6
13.9
9.0
―
―
10
―
Ta =
−40
to 85°C
Min
1.0
1.0
1.0
1.0
60
90
―
―
Max
16.6
11.0
16.0
10.4
―
―
10
―
ns
Unit
t
pHL
―
ns
MHz
pF
pF
Note:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
= C
PD
·V
CC
·f
IN
+ I
CC
/6 (per F/F)
And the total C
PD
when n pcs of flip flop operate can be gained by the following equation:
C
PD
(total) = 34 + 40·n
5
2007-10-01
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