eGaN® FET DATASHEET
EPC2007
EPC2007 – Enhancement Mode Power Transistor
V
DSS
, 100 V
R
DS(ON)
, 30 mW
I
D
, 6 A
NEW PRODUCT
EFFICIENT POWER CONVERSION
HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag-
ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-
tron mobility and low temperature coefficient allows very low R
DS(ON)
, while its lateral device structure
and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are beneficial as well as
those where on-state losses dominate.
Maximum Ratings
V
DS
I
D
V
GS
T
J
T
STG
Drain-to-Source Voltage (Continuous)
Drain-to-Source Voltage (up to 10,000 5ms pulses at 125° C)
Continuous (T
A
= 25˚C,
θ
JA
= 40)
Pulsed (25˚C, Tpulse = 300 µs)
Gate-to-Source Voltage
Gate-to-Source Voltage
Operating Temperature
Storage Temperature
100
120
6
25
6
-5
-40 to 125
-40 to 150
V
V
A
V
˚C
EPC2007 eGaN® FETs are supplied only in
passivated die form with solder bumps
Applications
• High Speed DC-DC conversion
• Class D Audio
• Hard Switched and High Frequency Circuits
Benefits
• Ultra High Efficiency
• Ultra Low R
DS(on)
• Ultra low Q
G
• Ultra small footprint
PARAMETER
Static Characteristics
(T
J
= 25˚C unless otherwise stated)
BV
DSS
I
DSS
I
GSS
V
GS(th)
R
DS(ON)
Drain-to-Source Voltage
Drain Source Leakage
Gate-Source Forward Leakage
Gate-Source Reverse Leakage
Gate Threshold Voltage
Drain-Source On Resistance
TEST CONDITIONS
V
GS
= 0 V, I
D
= 75 µA
V
DS
= 80 V, V
GS
= 0 V
V
GS
= 5 V
V
GS
= -5 V
V
DS
= V
GS
, I
D
= 1.2 mA
V
GS
= 5 V, I
D
= 6 A
MIN
100
TYP
MAX
UNIT
V
20
0.25
0.1
0.7
1.4
24
60
2
0.5
2.5
30
µA
mA
V
mΩ
Source-Drain Characteristics
(T
J
= 25˚C unless otherwise stated)
V
SD
Source-Drain Forward Voltage
I
S
= 0.5 A, V
GS
= 0 V, T = 25˚C
I
S
= 0.5 A, V
GS
= 0 V, T = 125˚C
1.77
1.82
V
All measurements were done with substrate shorted to source.
Thermal Characteristics
TYP
R
θ
JC
R
θ
JB
R
θ
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Board
Thermal Resistance, Junction to Ambient (Note 1)
6.9
32
80
˚C/W
˚C/W
˚C/W
Note 1: R
θ
JA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION |
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| COPYRIGHT 2013 |
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eGaN® FET DATASHEET
EPC2007
PARAMETER
Dynamic Characteristics
(T
J
= 25˚C unless otherwise stated)
C
ISS
C
OSS
C
RSS
Q
G
Q
GD
Q
GS
Q
OSS
Q
RR
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge (V
GS
= 5 V)
Gate-to-drain Charge
Gate-to Source Charge
Output Charge
Source-Drain Recovery Charge
TEST CONDITIONS
MIN
TYP
205
MAX
240
140
8.2
2.8
1.2
0.70
15.3
UNIT
V
DS
= 50 V, V
GS
= 0 V
118
6.6
2.1
pF
V
DS
= 50 V, I
D
= 6 A
V
DS
= 50 V, V
GS
= 0 V
0.61
0.52
10.2
0
nC
All measurements were done with substrate shorted to source.
40
35
30
Figure 1: Typical Output Characteristics
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
40
35
30
Figure 2: Transfer Characteristics
25˚C
125˚C
V
DS
= 3V
I
D
Drain Current (A)
25
20
15
10
5
0
0
0.5
1
1.5
2
I
D
Drain Current (A)
25
20
15
10
5
0
.5
1
1.5
2
2.5
3
3.5
4
4.5
V
DS
– Drain to Source Voltage (V)
V
GS
– Gate to Source Voltage (V)
70
Figure 3: R
DS(ON)
vs. V
GS
for Various Current
R
DS(ON)
– Drain to Source Resistance (mΩ)
100
Figure 4: R
DS(ON)
vs. V
GS
for Various Temperature
25˚C
125˚C
I
D
= 6 A
R
DS(ON)
– Drain to Source Resistance (mΩ)
60
50
40
30
20
10
0
I
D
= 4 A
I
D
= 6 A
I
D
= 10 A
I
D
= 20 A
2
2.5
80
60
40
20
V
GS
– Gate to Source Voltage (V)
3
3.5
4
4.5
5
0
2
2.5
V
GS
– Gate to Source Voltage (V)
3
3.5
4
4.5
5
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| COPYRIGHT 2013 |
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eGaN® FET DATASHEET
Figure 5: Capacitance
5
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
EPC2007
Figure 6: Gate Charge
I
D
= 6 A
V
DS
= 50 V
0.4
0.35
0.3
0.25
0.2
V
GS
– Gate to Source Voltage (V)
100
4
C – Capacitance (nF)
3
0.15
0.1
0.05
0
0
20
40
60
80
2
1
0
V
DS
– Drain to Source Voltage (V)
0
0.5
Q
G
– Gate Charge (nC)
1
1.5
2
2.5
30
25
Figure 7: Reverse Drain-Source Characteristics
Normalized On-State Resistance – R
DS(ON)
25˚C
125˚C
Figure 8: Normalized On Resistance vs. Temperature
1.8
1.6
1.4
1.2
1
I
D
= 6 A
V
GS
= 5 V
I
SD
– Source to Drain Current (A)
20
15
10
5
0
0
0.5
1
V
SD
– Source to Drain Voltage (V)
1.5
2
2.5
3
3.5
4
0.8
-20
0
20
T
J
– Junction Temperature ( ˚C )
40
60
80
100
120
140
1.5
1.4
Figure 9: Normalized Threshold Voltage vs. Temperature
Figure 10: Gate Current
0.008
25˚C
125˚C
0.006
Normalized Threshold Voltage (V)
1.3
1.1
1
0.9
0.8
0.7
0.6
0.5
-20
I
D
= 1.2 mA
0
50
100
150
I
G
– Gate Current (A)
1.2
0.004
0.002
0
0
1
2
3
4
5
6
T
J
– Junction Temperature ( ˚C )
V
GS
– Gate-to-Source Voltage (V)
All measurements were done with substrate shortened to source.
EPC – EFFICIENT POWER CONVERSION CORPORATION |
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| COPYRIGHT 2013 |
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eGaN® FET DATASHEET
Figure 11: Transient Thermal Response Curves
Normalized Maximum Transient Thermal Impedance
Z
θJB
, Normalized Thermal Impedance
Duty Factors:
0.5
0.1
0.2
0.1
0.05
0.01
0.02
0.01
0.001
0.0001
Single Pulse
1
EPC2007
P
DM
t
1
t
2
Notes:
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJB
x R
θJB
+ T
B
10
-2
10
-1
1
10
100
t
p
, Rectangular Pulse Duration, seconds
10
-5
10
-4
10
-3
Normalized Maximum Transient Thermal Impedance
1
Z
θJC
, Normalized Thermal Impedance
Duty Factors:
0.5
0.1
0.2
0.1
0.05
0.01
0.02
0.01
Single Pulse
0.001
10
-6
10
-5
10
-4
10
-3
P
DM
t
1
t
2
Notes:
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-2
10
-1
1
t
p
, Rectangular Pulse Duration, seconds
Figure 12: Safe Operating Area
100
I
D
- Drain Current (A)
10
10 µs
100 µs
1 ms
10 ms
100 ms/DC
100
1
limited by R
DS(ON)
0.1
T
J
= Max Rated, T
C
= +25°C, Single Pulse
0.1
1
10
V
DS
- Drain-Source Voltage (V)
1000
EPC – EFFICIENT POWER CONVERSION CORPORATION |
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| COPYRIGHT 2013 |
| PAGE 4
eGaN® FET DATASHEET
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7” reel
EPC2007
b
d
e
f
g
Loaded Tape Feed Direction
7” reel
Die
orientation
dot
a
c
Gate
solder bar is
under this
corner
EPC2007 (note 1)
Dimension (mm)
target
min
max
Die is placed into pocket
solder bar side down
(face side down)
a
b
c (see note)
d
e
f (see note)
g
8.00
1.75
3.50
4.00
4.00
2.00
1.5
7.90
1.65
3.45
3.90
3.90
1.95
1.5
8.30
1.85
3.55
4.10
4.10
2.05
1.6
Note 1: MSL 1 (moisture sensitivity level 1) classi ed according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
2007
Die orientation dot
Gate Pad bump is
under this corner
YYYY
ZZZZ
Part
Number
EPC2007
Laser Markings
Part #
Marking Line 1
2007
Lot_Date Code
Marking line 2
YYYY
Lot_Date Code
Marking Line 3
ZZZZ
DIE OUTLINE
A
f
f
X3
Solder Bar View
DIM
A
B
c
d
e
f
g
MIN
1672
1057
834
327
235
195
400
MICROMETERS
Nominal
1702
1087
837
330
250
200
400
MAX
1732
1117
840
333
265
205
400
2
3
1
4
5
d
X2
c
e
g
g
X2
Side View
815 Max
(685)
SEATING PLANE
100 +/- 20
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2013 |
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| PAGE 5
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