EDB4416BBBH-1DIT-F-R TR datasheet, PDF

Datasheet> All Categories > storage> EDB4416BBBH-1DIT-F-R TR

EDB4416BBBH-1DIT-F-R TR: DescriptionIC DRAM 4G PARALLEL 134FBGA; Categorystorage; File Size12MB，137 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

Download Datasheet Parametric Compare View All

EDB4416BBBH-1DIT-F-R TR Overview

IC DRAM 4G PARALLEL 134FBGA

EDB4416BBBH-1DIT-F-R TR Parametric

Parameter Name	Attribute value
memory type	Volatile
memory format	DRAM
technology	SDRAM - Mobile LPDDR2
storage	4Gb （256M x 16）
Clock frequency	533MHz
Write cycle time - words, pages	-
memory interface	in parallel
Voltage - Power	1.14 V ~ 1.95 V
Operating temperature	-40°C ~ 85°C（TC）
Installation type	surface mount
Package/casing	134-WFBGA
Supplier device packaging	134-FBGA（10x11.5）

Preview

Download Datasheet

View All

Embedded LPDDR2 SDRAM

Features

Embedded LPDDR2 SDRAM

EDB4416BBBH, EDB4432BBBJ

Features

• Ultra-low-voltage core and I/O power supplies

• Frequency range

– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)

• 4n prefetch DDR architecture

• 8 internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on each CK_t/CK_c

edge

• Bidirectional/differential data strobe per byte of

data (DQS_t/DQS_c)

• Programmable READ and WRITE latencies (RL/WL)

• Burst length: 4, 8, and 16

• Per-bank refresh for concurrent operation

• Auto temperature-compensated self refresh

(ATCSR) by built-in temperature sensor

• Partial-array self refresh (PASR)

• Selectable output drive strength (DS)

• Clock-stop capability

• Lead-free (RoHS-compliant) and halogen-free

packaging

Table 1: Key Timing Parameters

Speed

Grade

Clock Rate Data Rate

(MHz)

(Mb/s/pin)

533

1066

Options

• Density/Page Size

– 4Gb / 1-CS - single die

• Organization

– x16

– x32

• V

DD1

DD2

DDQ

: 1.8V/1.2V/1.2V

• Revision

• FBGA “green” package

– 10mm x 11.5mm x 0.75mm, 134-

ball x16

– 10mm x 11.5mm x 0.75mm, 134-

ball x32

• Timing – cycle time

– 1.875ns @ RL = 8

• Operating temperature range

– From –30°C to +85°C

– From –40°C to +85°C

Marking

-1D

Blank

Table 2: S4 Configuration Addressing

Architecture

Die configuration

Row addressing

Column addressing

256 Meg x 16

32 Meg x 16 x 8 banks

16K A[13:0]

2K A[10:0]

128 Meg x 32

16 Meg x 32 x 8 banks

16K A[13:0]

1K A[9:0]

X26P4QTWDSPK-13-10166

134b_2e0e_embedded_lpddr2 – Rev. B 09/16 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Embedded LPDDR2 SDRAM

Features

Contents

LPDDR2 Array Configuration ............................................................................................................................ 9

General Notes .............................................................................................................................................. 9

Specifications – Single Die, Single Channel ................................................................................................ 10

Package Block Diagrams ................................................................................................................................. 13

Package Dimensions ....................................................................................................................................... 14

Ball Assignments ............................................................................................................................................ 15

Ball Descriptions ............................................................................................................................................ 17

Functional Description ................................................................................................................................... 18

Simplified State Diagram ................................................................................................................................ 19

Power-Up and Initialization ............................................................................................................................ 21

Voltage Ramp and Device Initialization ....................................................................................................... 21

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 23

Power-Off Sequence ....................................................................................................................................... 23

Uncontrolled Power-Off Sequence .............................................................................................................. 24

Mode Register Definition ................................................................................................................................ 24

Mode Register Assignments and Definitions ................................................................................................ 24

Commands and Timing .................................................................................................................................. 35

ACTIVATE Command ..................................................................................................................................... 36

8-Bank Device Operation ............................................................................................................................ 37

Read and Write Access Modes ......................................................................................................................... 38

Burst READ Command ................................................................................................................................... 38

READs Interrupted by a READ ..................................................................................................................... 45

Burst WRITE Command .................................................................................................................................. 45

WRITEs Interrupted by a WRITE ................................................................................................................. 48

BURST TERMINATE Command ...................................................................................................................... 48

Write Data Mask ............................................................................................................................................. 50

PRECHARGE Command ................................................................................................................................. 51

READ Burst Followed by PRECHARGE ......................................................................................................... 52

WRITE Burst Followed by PRECHARGE ....................................................................................................... 53

Auto Precharge operation ........................................................................................................................... 54

READ Burst with Auto Precharge ................................................................................................................. 54

WRITE Burst with Auto Precharge ............................................................................................................... 55

REFRESH Command ...................................................................................................................................... 57

REFRESH Requirements ............................................................................................................................. 59

SELF REFRESH Operation ............................................................................................................................... 66

Partial-Array Self Refresh – Bank Masking .................................................................................................... 68

Partial-Array Self Refresh – Segment Masking .............................................................................................. 68

MODE REGISTER READ ................................................................................................................................. 69

Temperature Sensor ................................................................................................................................... 71

DQ Calibration ........................................................................................................................................... 73

MODE REGISTER WRITE Command ............................................................................................................... 75

MRW RESET Command .............................................................................................................................. 75

MRW ZQ Calibration Commands ................................................................................................................ 76

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 78

Input Clock Frequency Changes and Stop Events ............................................................................................. 78

Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 78

Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 78

NO OPERATION Command ............................................................................................................................ 79

Truth Tables ................................................................................................................................................... 79

Absolute Maximum Ratings ............................................................................................................................ 87

X26P4QTWDSPK-13-10166

134b_2e0e_embedded_lpddr2 – Rev. B 09/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Embedded LPDDR2 SDRAM

Features

Input/Output Capacitance .............................................................................................................................. 87

Electrical Specifications – I

Specifications and Conditions ............................................................................ 88

AC and DC Operating Conditions .................................................................................................................... 91

AC and DC Logic Input Measurement Levels for Single-Ended Signals .............................................................. 92

REF

Tolerances .......................................................................................................................................... 93

Input Signal ............................................................................................................................................... 95

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................. 97

Single-Ended Requirements for Differential Signals ..................................................................................... 98

Differential Input Crosspoint Voltage ......................................................................................................... 100

Input Slew Rate ......................................................................................................................................... 101

Output Characteristics and Operating Conditions ........................................................................................... 101

Single-Ended Output Slew Rate .................................................................................................................. 102

Differential Output Slew Rate ..................................................................................................................... 103

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 105

Output Driver Impedance .............................................................................................................................. 106

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 107

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 108

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 108

Clock Specification ........................................................................................................................................ 111

CK(abs),

CH(abs), and

CL(abs) ................................................................................................................ 113

Clock Period Jitter .......................................................................................................................................... 113

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 113

Cycle Time Derating for Core Timing Parameters ........................................................................................ 114

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 114

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 114

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 114

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 115

Refresh Requirements Parameters .................................................................................................................. 116

AC Timing ..................................................................................................................................................... 116

CA and CS_n Setup, Hold, and Derating .......................................................................................................... 122

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 130

Revision History ............................................................................................................................................ 137

Rev. B – 09/16 ............................................................................................................................................ 137

Rev. A – 02/16 ............................................................................................................................................ 137

X26P4QTWDSPK-13-10166

134b_2e0e_embedded_lpddr2 – Rev. B 09/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Embedded LPDDR2 SDRAM

Features

List of Figures

Figure 1: LPDDR2 Part Numbering ................................................................................................................... 2

Figure 2: Single-Rank Single-Channel Package Block Diagram ........................................................................ 13

Figure 3: 134-Ball FBGA (10mm x 11.5mm x 0.75mm) ..................................................................................... 14

Figure 4: 134-Ball FBGA (x16) ......................................................................................................................... 15

Figure 5: 134-Ball FBGA (x32) ......................................................................................................................... 16

Figure 6: Functional Block Diagram ............................................................................................................... 19

Figure 7: Simplified State Diagram ................................................................................................................. 20

Figure 8: Voltage Ramp and Initialization Sequence ........................................................................................ 23

Figure 9: Command and Input Setup and Hold ............................................................................................... 36

Figure 10: CKE Input Setup and Hold ............................................................................................................. 36

Figure 11: ACTIVATE Command .................................................................................................................... 37

Figure 12:

FAW Timing (8-Bank Devices) ....................................................................................................... 38

Figure 13: READ Output Timing –

DQSCK (MAX) ........................................................................................... 39

Figure 14: READ Output Timing –

DQSCK (MIN) ........................................................................................... 39

Figure 15: Burst READ – RL = 5, BL = 4,

DQSCK >

CK ..................................................................................... 40

Figure 16: Burst READ – RL = 3, BL = 8,

DQSCK <

CK ..................................................................................... 40

Figure 17:

DQSCKDL Timing ........................................................................................................................ 41

Figure 18:

DQSCKDM Timing ....................................................................................................................... 42

Figure 19:

DQSCKDS Timing ......................................................................................................................... 43

Figure 20: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 44

Figure 21: Seamless Burst READ – RL = 3, BL = 4,

CCD = 2 .............................................................................. 44

Figure 22: READ Burst Interrupt Example – RL = 3, BL = 8,

CCD = 2 ................................................................. 45

Figure 23: Data Input (WRITE) Timing ........................................................................................................... 46

Figure 24: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 46

Figure 25: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 47

Figure 26: Seamless Burst WRITE – WL = 1, BL = 4,

CCD = 2 ............................................................................ 47

Figure 27: WRITE Burst Interrupt Timing – WL = 1, BL = 8,

CCD = 2 ................................................................ 48

Figure 28: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 49

Figure 29: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 50

Figure 30: Data Mask Timing ......................................................................................................................... 50

Figure 31: Write Data Mask – Second Data Bit Masked .................................................................................... 51

Figure 32: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(

RTP(MIN)/

CK) = 2 ................................ 52

Figure 33: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 3 ................................ 53

Figure 34: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 54

Figure 35: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 2 ........................................ 55

Figure 36: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 56

Figure 37:

SRF Definition .............................................................................................................................. 60

Figure 38: Regular Distributed Refresh Pattern ............................................................................................... 62

Figure 39: Supported Transition from Repetitive REFRESH Burst .................................................................... 63

Figure 40: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 64

Figure 41: Recommended Self Refresh Entry and Exit ..................................................................................... 65

Figure 42: All-Bank REFRESH Operation ........................................................................................................ 66

Figure 43: Per-Bank REFRESH Operation ....................................................................................................... 66

Figure 44: SELF REFRESH Operation .............................................................................................................. 67

Figure 45: MRR Timing – RL = 3,

MRR = 2 ...................................................................................................... 69

Figure 46: READ to MRR Timing – RL = 3,

MRR = 2 ......................................................................................... 70

Figure 47: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 71

Figure 48: Temperature Sensor Timing ........................................................................................................... 73

Figure 49: MR32 and MR40 DQ Calibration Timing – RL = 3,

MRR = 2 ............................................................. 74

Figure 50: MODE REGISTER WRITE Timing – RL = 3,

MRW = 5 ....................................................................... 75

X26P4QTWDSPK-13-10166

134b_2e0e_embedded_lpddr2 – Rev. B 09/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDB4416BBBH-1DIT-F-R TR Related Products

	EDB4416BBBH-1DIT-F-R TR	EDB4416BBBH-1DIT-F-R	EDB4432BBBJ-1D-F-R	EDB4416BBBH-1DIT-F-D	EDB4432BBBJ-1D-F-D	EDB4432BBBJ-1DAIT-F-D	EDB4432BBBJ-1DAAT-F-R TR	EDB4432BBBJ-1DAIT-F-R TR	EDB4416BBBH-1DIT-F
Description	IC DRAM 4G PARALLEL 134FBGA	IC DRAM 4G PARALLEL 533MHZ	IC DRAM 4G PARALLEL 134FBGA	IC DRAM 4G PARALLEL 134FBGA	IC DRAM 4G PARALLEL 134FBGA	IC DRAM 4G PARALLEL 134FBGA	IC DRAM 4G PARALLEL 134FBGA	IC DRAM 4G PARALLEL 134FBGA	DDR DRAM, 256MX16, CMOS, PBGA134, WFBGA-134
technology	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	CMOS	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	CMOS
memory type	Volatile	Volatile	Volatile	Volatile	Volatile	-	Volatile	Volatile	-
memory format	DRAM	DRAM	DRAM	DRAM	DRAM	-	DRAM	DRAM	-
storage	4Gb （256M x 16）	4Gb （256M x 16）	4Gb （128M x 32）	4Gb （256M x 16）	4Gb （128M x 32）	-	4Gb （128M x 32）	4Gb （128M x 32）	-
Clock frequency	533MHz	533MHz	533MHz	533MHz	533MHz	-	533MHz	533MHz	-
memory interface	in parallel	in parallel	in parallel	in parallel	in parallel	-	in parallel	in parallel	-
Voltage - Power	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	-	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	-
Operating temperature	-40°C ~ 85°C（TC）	-40°C ~ 85°C（TC）	-30°C ~ 85°C（TC）	-40°C ~ 85°C（TC）	-30°C ~ 85°C（TC）	-	-40°C ~ 105°C（TC）	-40°C ~ 85°C（TC）	-
Installation type	surface mount	-	surface mount	surface mount	surface mount	-	surface mount	surface mount	-
Package/casing	134-WFBGA	-	134-WFBGA	134-WFBGA	134-WFBGA	-	134-WFBGA	134-WFBGA	-
Supplier device packaging	134-FBGA（10x11.5）	-	134-FBGA（10x11.5）	134-FBGA（10x11.5）	134-FBGA（10x11.5）	-	134-FBGA（10x11.5）	134-FBGA（10x11.5）	-

Recommended Resources

Varactor Diode Frequency Modulator

DC relay delayed release circuit 2b

Series voltage regulator circuit diagram with adjustable output voltage

Using autotransformer and time relay to start control circuit

astable circuit

Computer motherboard circuit diagram 815 2_38

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components