GS81302DT10E-350 datasheet, PDF

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GS81302DT10E-350: DescriptionStatic random access memory 1.8 or 1.5V 16M x 9 144M; Categorystorage storage; File Size2MB，31 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS81302DT10E-350 Overview

Static random access memory 1.8 or 1.5V 16M x 9 144M

GS81302DT10E-350 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Factory Lead Time	12 weeks
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	150994944 bit
Memory IC Type	QDR SRAM
memory width	9
Number of functions	1
Number of terminals	165
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX9
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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GS81302DT07/10/19/37E-450/400/350/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

144Mb SigmaQuad-II+

Burst of 4 SRAM

450 MHz–300 MHz

1.8 V V

1.8 V and 1.5 V I/O

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS81302DT07/10/19/37E SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 16M x 8 has a

4M addressable index).

SigmaQuad™ Family Overview

The GS81302DT07/10/19/37E are built in compliance with

the SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302DT07/10/19/37E SigmaQuad SRAMs

Parameter Synopsis

-450

tKHKH

tKHQV

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.00b 8/2017

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Description	Static random access memory 1.8 or 1.5V 16M x 9 144M	Static random access memory 1.8 or 1.5V 8M x 18 144M	Static random access memory 1.8 or 1.5V 4M x 36 144M	Static random access memory 1.8 or 1.5V 8M x 18 144M	Static random access memory 1.8 or 1.5V 8M x 18 144M	Static random access memory 1.8 or 1.5V 8M x 18 144M	Static random access memory 1.8 or 1.5V 8M x 18 144M	Static random access memory 1.8 or 1.5V 16M x 9 144M	Static random access memory 1.8 or 1.5V 16M x 9 144M
Maker	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology
Maximum operating temperature	70 °C	70 °C	85 °C	85 °C	+ 70 C	85 °C	85 °C	85 °C	70 °C
Minimum operating temperature	-	-	-40 °C	-40 °C	0 C	-40 °C	-40 °C	-40 °C	-
organize	16MX9	8MX18	4MX36	8MX18	8 M x 18	8MX18	8MX18	16MX9	16MX9
Is it lead-free?	Contains lead	Lead free	Lead free	Contains lead	-	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	incompatible	conform to	conform to	incompatible	-	conform to	conform to	conform to	conform to
Parts packaging code	BGA	BGA	BGA	BGA	-	BGA	BGA	BGA	BGA
package instruction	LBGA,	LBGA,	LBGA,	LBGA,	-	LBGA,	LBGA,	LBGA,	LBGA,
Contacts	165	165	165	165	-	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant	-	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	-	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Factory Lead Time	12 weeks	12 weeks	12 weeks	12 weeks	-	12 weeks	12 weeks	12 weeks	12 weeks
Maximum access time	0.45 ns	0.45 ns	0.45 ns	0.45 ns	-	0.45 ns	0.45 ns	0.45 ns	0.45 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	-	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
length	17 mm	17 mm	17 mm	17 mm	-	17 mm	17 mm	17 mm	17 mm
memory density	150994944 bit	150994944 bit	150994944 bit	150994944 bit	-	150994944 bit	150994944 bit	150994944 bit	150994944 bit
Memory IC Type	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM	-	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM
memory width	9	18	36	18	-	18	18	9	9
Number of functions	1	1	1	1	-	1	1	1	1
Number of terminals	165	165	165	165	-	165	165	165	165
word count	16777216 words	8388608 words	4194304 words	8388608 words	-	8388608 words	8388608 words	16777216 words	16777216 words
character code	16000000	8000000	4000000	8000000	-	8000000	8000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	-	LBGA	LBGA	LBGA	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	-	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	260	NOT SPECIFIED	-	260	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.5 mm	1.5 mm	1.5 mm	-	1.5 mm	1.5 mm	1.5 mm	1.5 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	-	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	-	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	-	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	-	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	-	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	-	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	15 mm	15 mm	15 mm	15 mm	-	15 mm	15 mm	15 mm	15 mm
JESD-609 code	-	e1	e1	-	-	e1	e1	e1	e1
Humidity sensitivity level	-	3	3	-	-	3	3	3	3
Terminal surface	-	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	-	-	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)

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