Features ............................................................................................................................................................... 7
1.2.2. Data Link Layer ...............................................................................................................................................7
1.2.4. Configuration Space Support ..........................................................................................................................8
1.2.5. Top Level IP Support .......................................................................................................................................8
Using the Transmit and Receive Interfaces ....................................................................................................... 28
2.3.1. As a Completer .............................................................................................................................................28
2.3.2. As a Requestor ..............................................................................................................................................29
Configuration Space .......................................................................................................................................... 31
2.5.1. Base Configuration Type0 Registers .............................................................................................................31
2.5.2. Power Management Capability Structure ....................................................................................................31
2.5.4. How to Enable/Disable MSI ..........................................................................................................................31
2.5.5. How to issue MSI ..........................................................................................................................................31
General Tab ....................................................................................................................................................... 42
Flow Control Tab ............................................................................................................................................... 44
3.4.
Configuration Space - 1 Tab .............................................................................................................................. 45
3.5.
Configuration Space - 2 Tab .............................................................................................................................. 47
4. IP Core Generation and Evaluation ............................................................................................................................. 50
4.1.
Licensing the IP Core ......................................................................................................................................... 50
4.1.1. Licensing Requirements for ECP5 and ECP5-5G ...........................................................................................50
4.2.
IPexpress Flow for LatticeECP3 Devices ............................................................................................................ 50
4.2.1. Getting Started .............................................................................................................................................50
4.2.2. IPexpress-Created Files and Top Level Directory Structure .........................................................................52
4.2.3. Instantiating the Core ...................................................................................................................................53
4.2.7. Enabling Hardware Evaluation in Diamond ..................................................................................................55
4.2.8. Updating/Regenerating the IP Core .............................................................................................................55
4.2.9. Regenerating an IP Core in Diamond............................................................................................................55
4.3.
Clarity Designer Flow for ECP5 and ECP5-5G Devices ....................................................................................... 55
4.3.1. Getting Started .............................................................................................................................................55
4.3.2. Configuring and Placing the IP Core .............................................................................................................57
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
FPGA-IPUG-02009-1.8
PCI Express x1/x2/x4 Endpoint IP Core
User Guide
4.3.3. Generating the IP Core ................................................................................................................................. 60
4.3.4. Clarity Designer-Created Files and Directory Structure ............................................................................... 60
4.3.5. Instantiating the Core ................................................................................................................................... 62
4.3.9. Updating/Regenerating the IP Core ............................................................................................................. 63
5. Using the IP Core ........................................................................................................................................................ 65
5.1.
Simulation and Verification ............................................................................................................................... 65
5.1.2. Alternative Testbench Approach .................................................................................................................. 65
5.1.3. Third Party Verification IP ............................................................................................................................ 66
5.2.
FPGA Design Implementation for LatticeECP3 Devices..................................................................................... 67
5.2.1. Setting Up the Core ...................................................................................................................................... 67
5.2.2. Setting Up for Native x4 (No Flip) ................................................................................................................. 67
5.2.3. Setting Up for Native x4 (Flipped) ................................................................................................................ 67
5.2.4. Setting Up for Downgraded x1 (No Flip) ...................................................................................................... 67
5.2.5. Setting Up for Downgraded x1 (Flipped) ...................................................................................................... 68
5.2.8. Locating the IP .............................................................................................................................................. 69
5.3.
Board-Level Implementation Information ........................................................................................................ 70
5.5.1. LatticeECP3 and ECP5 IP Simulation ............................................................................................................. 75
ECP5 and ECP5-5G .......................................................................................................................................................... 77
Technical Support Assistance ............................................................................................................................................. 78
Appendix A. Resource Utilization of 2.5G IP Core .............................................................................................................. 79
Appendix B. Resource Utilization of PCI Express 5G IP Core .............................................................................................. 81
Revision History .................................................................................................................................................................. 82
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02009_1.8
3
PCI Express x1/x2/x4 Endpoint IP Core
User Guide
Figures
Figure 2.1. PCI Express IP Core Technology and Functions ...................................................................................................9
Figure 2.2. PCI Express Core Implementation in LatticeECP3, ECP5 and EPC5-5G .............................................................10
Figure 3.1. PCI Express IP Core General Options .................................................................................................................42
Figure 3.2. PCI Express IP Core PCS Pipe Options.................................................................................................................43
Figure 3.4. PCI Express IP Core Configuration Space - 1 Options ........................................................................................45
Figure 3.5. PCI Express IP Core Configuration Space - 2 Options ........................................................................................47
Figure 4.12. Generating the IP Core ...................................................................................................................................60
Figure 5.6. LatticeECP3 Device Arrays with PCS/SERDES ....................................................................................................70
Figure 5.7. ECP5 Device Arrays with PCS/SERDES ...............................................................................................................70
Figure 5.8. Best Case Timing Diagram, Lattice Device with Respect to PERST# .................................................................71
Figure 5.9. Worst Case Timing Diagram, Lattice Device with Respect to PERST#...............................................................71
Figure 5.10. Example of Board Layout Concern with x4 Link ..............................................................................................72
Figure 5.11. Implementation of x4 IP Core to Edge Fingers ...............................................................................................73
Figure 5.12. Implementation of x1 IP Core to Edge Fingers ...............................................................................................74
Figure 5.13. PCI Express Endpoint Add In Card ...................................................................................................................74
Table 2.1. PCI Express IP Core Port List............................................................................................................................... 11
Table 2.2. Unsupported TLPs Which Can be Received by the IP ........................................................................................ 30
Table 2.3. Unsupported TLPs Which Can Be Received by the IP ........................................................................................ 32
Table 2.5. Physical Layer Error List ..................................................................................................................................... 34
Table 2.6. Data Link Layer Error List ................................................................................................................................... 34
Table 2.7. Transaction Layer Error List ............................................................................................................................... 35
Table 3.1. IP Core Parameters ............................................................................................................................................ 40
Table 3.2. General Tab Parameters .................................................................................................................................... 43
Table 3.4. Flow Control Tab Parameters ............................................................................................................................ 44
Table 3.5. Configuration Space - 1 Tab Parameters............................................................................................................ 46
Table 3.6. Configuration Space - 2 Tab Parameters............................................................................................................ 47
Table 3.7. Total EBR Count Based on Max Payload Size (2.5G IP Core) .............................................................................. 49
Table 4.1. File List ............................................................................................................................................................... 52
Table 4.2. File List ............................................................................................................................................................... 61
Table 5.1. LatticeECP3 Power Up Timing Specifications ..................................................................................................... 72
Table 5.2. ECP5 Power Up Timing Specifications ................................................................................................................ 72
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