NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX28CEC
Rev. 4,
10/2018
i.MX28
i.MX28 Applications
Processors for Consumer
Products
Package Information
Plastic package
Case MAPBGA-289, 14 x 14 mm, 0.8 mm pitch
Ordering Information
See
Table on page 3
for ordering information.
1
Introduction
1
The i.MX28 is a low-power, high-performance
applications processor optimized for the general
embedded industrial and consumer markets. The core of
the i.MX28 is NXP's fast, power-efficient
implementation of the ARM926EJ-S™ core, with
speeds of up to 454 MHz.
The device is suitable for a wide range of applications,
including the following:
• Human-machine interface (HMI) panels:
industrial, home
• Industrial drive, PLC, I/O control display, factory
robotics display, graphical remote controls
• Handheld scanners and printers
• Patient-monitoring, portable medical devices
• Smart energy meters, energy gateways
• Media phones, media gateways
The integrated power management unit (PMU) on the
i.MX28 is composed of a triple output DC-DC switching
converter and multiple linear regulators. These provide
NXP reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Ordering Information and Functional
Part Differences
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Special Signal Considerations. . . . . . . . . . . . . . . . 11
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 i.MX28 Device-Level Conditions . . . . . . . . . . . . . . 11
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 18
3.3 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 I/O AC Timing and Parameters . . . . . . . . . . . . . . . 22
3.5 Module Timing and Electrical Parameters. . . . . . . 27
Package Information and Contact Assignments . . . . . . . 59
4.1 Case MAPBGA-289, 14 x 14 mm, 0.8 mm Pitch. . 59
4.2 Ground, Power, Sense, and Reference Contact
Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3 Signal Contact Assignments . . . . . . . . . . . . . . . . . 61
4.4 i.MX280 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.5 i.MX283 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.6 i.MX286 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7 i.MX287 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 69
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Introduction
power sequencing for the device and its I/O peripherals such as memories and SD cards, as well as provide
battery charging capability for Li-Ion batteries.
The i.MX28 processor includes an additional 128-Kbyte on-chip SRAM to make the device ideal for
eliminating external RAM in applications with small footprint RTOS.
The i.MX28 supports connections to various types of external memories, such as mobile DDR, DDR2 and
LV-DDR2, SLC and MLC NAND Flash.
The i.MX28 can be connected to a variety of external devices such as high-speed USB2.0 OTG, CAN,
10/100 Ethernet, and SD/SDIO/MMC.
1.1
Device Features
The following lists the features of the i.MX28:
• ARM926EJ-S CPU running at 454 MHz:
— 16-Kbyte instruction cache and 32-Kbyte data cache
— Arm embedded trace macrocell (CoreSight™ ETM9™)
— Parallel JTAG interface
• 128 KBytes of integrated low-power on-chip SRAM
• 128 KBytes of integrated mask-programmable on-chip ROM
• 1280 bits of on-chip one-time-programmable (OCOTP) ROM
• 16-bit mobile DDR (mDDR) (1.8 V), DDR2 (1.8 V) and LV-DDR2 (1.5 V), up to 205 MHz DDR
clock frequency with voltage overdrive
• Support for up to eight NAND Flash memory devices with up to 20-bit BCH ECC
• Four synchronous serial ports (SSP) for SDIO/MMC/MS/SPI: SSP0, SSP1, SSP2, and SSP3. SSP0
and SSP1 can support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only
1-bit and 4-bit modes.
• 10/100-Mbps Ethernet MAC compatible with IEEE Std 802.3™:
— Single 10/100 Ethernet with GMII/RMII or Dual 10/100 Ethernet with RMII interface
— Supporting IEEE Std 1588™-compatible hardware timestamp
— Supporting 50-MHz/25-MHz clock output for external Ethernet PHY
• Two 2.0B protocol-compatible Controller Area Network (CAN) interfaces
• One USB2.0 OTG device/host controller and PHY
• One USB2.0 host controller and PHY
• LCD controller, up to 24-bit RGB (DOTCK) modes and 24-bit system-mode
• Pixel-processing pipeline (PXP) supports full path from color-space conversion, scaling,
alpha-blending to rotation without intermediate memory access.
• SPDIF transmitter
• Dual serial audio interface (SAIF) to support full-duplex transmit and receive operations; each
SAIF supports three stereo pairs
i.MX28 Applications Processors for Consumer Products, Rev. 4,
10/2018
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NXP Semiconductors
Introduction
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Five application Universal Asynchronous Receiver-Transmitters (UARTs), up to 3.25 Mbps with
hardware flow control
One debug UART operating at up to 115 Kb/s using programmed I/O
Two I
2
C master/slave interfaces, up to 400 kbps
Four 32-bit timers and a rotary decoder
Eight Pulse Width Modulators (PWMs)
Real-time clock (RTC)
GPIO with interrupt capability
Power Management Unit (PMU) supports a triple output DC-DC switching converter, multiple
linear regulators, battery charger, and detector.
16-channel Low-Resolution A/D Converter (LRADC). There are 16 physical channels but they can
only be mapped to 8 virtual channels at a time.
Single channel High Speed A/D Converter (HSADC), up to 2 Msps data rate
4/5-wire touchscreen controller
Up to 8X8 keypad matrix with button-detect circuit
Security features:
— Read-only unique ID for Digital Rights Management (DRM) algorithms
— Secure boot using 128-bit AES hardware decryption
— SHA-1 and SHA256 hashing hardware
— High assurance boot (HAB4)
Offered in 289-pin Ball Grid Array (BGA)
1.2
Ordering Information and Functional Part Differences
Table 1.
Ordering Information
Part Number
MCIMX280DVM4B
MCIMX280DVM4C
MCIMX280CVM4B
MCIMX280CVM4C
MCIMX283DVM4B
MCIMX283DVM4C
MCIMX283CVM4B
MCIMX283CVM4C
MCIMX286DVM4B
MCIMX286DVM4C
Projected Temperature Range (°C)
–20 to +70
–20 to +70
–40 to +85
–40 to +85
–20 to +70
–20 to +70
–40 to +85
–40 to +85
–20 to +70
–20 to +70
Package
14 x 14 mm, 0.8mm pitch, MAPBGA-289
14 x 14 mm, 0.8mm pitch, MAPBGA-289
14 x 14 mm, 0.8mm pitch, MAPBGA-289
14 x 14 mm, 0.8mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
Table 1
provides the ordering information for the i.MX28.
i.MX28 Applications Processors for Consumer Products, Rev. 4,
10/2018
NXP Semiconductors
3
Introduction
Table 1.
Ordering Information
(continued)
Part Number
MCIMX286CVM4B
MCIMX286CVM4C
MCIMX287CVM4B
MCIMX287CVM4C
Projected Temperature Range (°C)
–40 to +85
–40 to +85
–40 to +85
–40 to +85
Package
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
14 x 14 mm, 0.8 mm pitch, MAPBGA-289
Table 2
provides the functional differences between the i.MX280, i.MX283, i.MX286, and i.MX287.
Table 2. i.MX28 Functional Differences
Function
Application UART
Debug UART
CAN
Ethernet
High-speed ADC
L2 Switch
LCD Interface
LRADC
1
PWM
S/PDIF Tx
SD/SDIO/MMC
2
Security
SPI
Touch Screen
USB 2.0
i.MX280
x5
x1
—
x1
x1
—
—
x8
x8
—
x4
Yes
x4
—
OTG HS with
HS PHY x1
HS Host with
HS PHY x1
1
2
i.MX283
x5
x1
—
x1
x1
—
Yes
x8
x8
—
x4
Yes
x4
Yes
OTG HS with HS PHY x1
HS Host with HS PHY x1
i.MX286
x5
x1
x2
x1
x1
—
Yes
x8
x8
Yes
x4
Yes
x4
Yes
OTG HS with HS PHY x1
HS Host with HS PHY x1
i.MX287
x5
x1
x2
x2
x1
Yes
Yes
x8
x8
Yes
x4
Yes
x4
Yes
OTG HS with HS PHY x1
HS Host with HS PHY x1
There are 16 physical channels but they can only be mapped to 8 virtual channels at a time.
For SD/SDIO/MMC, four synchronous serial ports (SSP) are available: SSP0, SSP1, SSP2, and SSP3. SSP0 and SSP1 can
support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only 1-bit and 4-bit modes.
i.MX28 Applications Processors for Consumer Products, Rev. 4,
10/2018
4
NXP Semiconductors
Introduction
1.3
Block Diagram
Figure 1
shows the simplified interface block diagram.
Figure 1. i.MX28 Simplified Interface Block Diagram
i.MX28 Applications Processors for Consumer Products, Rev. 4,
10/2018
NXP Semiconductors
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